[PATCH] drm/msm/dsi: don't allow enabling 14nm VCO with unprogrammed rate

[Dmitry Baryshkov]

On 01/05/2023 15:37, Konrad Dybcio wrote:
> 
> 
> On 1.05.2023 03:12, Dmitry Baryshkov wrote:
>> If the dispcc uses CLK_OPS_PARENT_ENABLE (e.g. on QCM2290), CCF can try
>> enabling VCO before the rate has been programmed. This can cause clock
>> lockups and/or other boot issues. Program the VCO to the minimal PLL
>> rate if the read rate is 0 Hz.
>>
>> Cc: Konrad Dybcio <konrad.dybcio at linaro.org>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>> ---
> Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy at linaro.org>
> Reported-by: Konrad Dybcio <konrad.dybcio at linaro.org>
> 
> I think this should also be implemented on other PLL gens.
> 
>>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> index 9f488adea7f5..3ce45b023e63 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
>> @@ -539,6 +539,9 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
>>   	if (unlikely(pll_14nm->phy->pll_on))
>>   		return 0;
>>   
>> +	if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0)
>> +		dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE);
> VCO_REF_CLK_RATE ---> phy->cfg->min_pll_rate (VCO_MIN_RATE)?

No, this is the parent rate, which is VCO_REF_CLK_RATE for all practical 
purposes.

> 
> Konrad
>> +
>>   	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
>>   	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
>>   

-- 
With best wishes
Dmitry