[PATCH v3 1/9] drm/msm/dpu: fix SSPP register definitions

[Jeykumar Sankaran]

On 5/18/2023 3:22 PM, Dmitry Baryshkov wrote:
> Reorder SSPP register definitions to sort them in the ascending order.
> Move register bitfields after the register definitions.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
Reviewed-by: Jeykumar Sankaran <quic_jeykumar at quicinc.com>
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 64 ++++++++++-----------
>   1 file changed, 32 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 6b68ec5c7a5a..08098880b7d5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -26,45 +26,18 @@
>   #define SSPP_SRC_FORMAT                    0x30
>   #define SSPP_SRC_UNPACK_PATTERN            0x34
>   #define SSPP_SRC_OP_MODE                   0x38
> -
> -/* SSPP_MULTIRECT*/
> -#define SSPP_SRC_SIZE_REC1                 0x16C
> -#define SSPP_SRC_XY_REC1                   0x168
> -#define SSPP_OUT_SIZE_REC1                 0x160
> -#define SSPP_OUT_XY_REC1                   0x164
> -#define SSPP_SRC_FORMAT_REC1               0x174
> -#define SSPP_SRC_UNPACK_PATTERN_REC1       0x178
> -#define SSPP_SRC_OP_MODE_REC1              0x17C
> -#define SSPP_MULTIRECT_OPMODE              0x170
> -#define SSPP_SRC_CONSTANT_COLOR_REC1       0x180
> -#define SSPP_EXCL_REC_SIZE_REC1            0x184
> -#define SSPP_EXCL_REC_XY_REC1              0x188
> -
> -#define MDSS_MDP_OP_DEINTERLACE            BIT(22)
> -#define MDSS_MDP_OP_DEINTERLACE_ODD        BIT(23)
> -#define MDSS_MDP_OP_IGC_ROM_1              BIT(18)
> -#define MDSS_MDP_OP_IGC_ROM_0              BIT(17)
> -#define MDSS_MDP_OP_IGC_EN                 BIT(16)
> -#define MDSS_MDP_OP_FLIP_UD                BIT(14)
> -#define MDSS_MDP_OP_FLIP_LR                BIT(13)
> -#define MDSS_MDP_OP_BWC_EN                 BIT(0)
> -#define MDSS_MDP_OP_PE_OVERRIDE            BIT(31)
> -#define MDSS_MDP_OP_BWC_LOSSLESS           (0 << 1)
> -#define MDSS_MDP_OP_BWC_Q_HIGH             (1 << 1)
> -#define MDSS_MDP_OP_BWC_Q_MED              (2 << 1)
> -
>   #define SSPP_SRC_CONSTANT_COLOR            0x3c
>   #define SSPP_EXCL_REC_CTL                  0x40
>   #define SSPP_UBWC_STATIC_CTRL              0x44
> -#define SSPP_FETCH_CONFIG                  0x048
> +#define SSPP_FETCH_CONFIG                  0x48
>   #define SSPP_DANGER_LUT                    0x60
>   #define SSPP_SAFE_LUT                      0x64
>   #define SSPP_CREQ_LUT                      0x68
>   #define SSPP_QOS_CTRL                      0x6C
> -#define SSPP_DECIMATION_CONFIG             0xB4
>   #define SSPP_SRC_ADDR_SW_STATUS            0x70
>   #define SSPP_CREQ_LUT_0                    0x74
>   #define SSPP_CREQ_LUT_1                    0x78
> +#define SSPP_DECIMATION_CONFIG             0xB4
>   #define SSPP_SW_PIX_EXT_C0_LR              0x100
>   #define SSPP_SW_PIX_EXT_C0_TB              0x104
>   #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS      0x108
> @@ -81,11 +54,33 @@
>   #define SSPP_TRAFFIC_SHAPER_PREFILL        0x150
>   #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL   0x154
>   #define SSPP_TRAFFIC_SHAPER_REC1           0x158
> +#define SSPP_OUT_SIZE_REC1                 0x160
> +#define SSPP_OUT_XY_REC1                   0x164
> +#define SSPP_SRC_XY_REC1                   0x168
> +#define SSPP_SRC_SIZE_REC1                 0x16C
> +#define SSPP_MULTIRECT_OPMODE              0x170
> +#define SSPP_SRC_FORMAT_REC1               0x174
> +#define SSPP_SRC_UNPACK_PATTERN_REC1       0x178
> +#define SSPP_SRC_OP_MODE_REC1              0x17C
> +#define SSPP_SRC_CONSTANT_COLOR_REC1       0x180
> +#define SSPP_EXCL_REC_SIZE_REC1            0x184
> +#define SSPP_EXCL_REC_XY_REC1              0x188
>   #define SSPP_EXCL_REC_SIZE                 0x1B4
>   #define SSPP_EXCL_REC_XY                   0x1B8
> -#define SSPP_VIG_OP_MODE                   0x0
> -#define SSPP_VIG_CSC_10_OP_MODE            0x0
> -#define SSPP_TRAFFIC_SHAPER_BPC_MAX        0xFF
> +
> +/* SSPP_SRC_OP_MODE & OP_MODE_REC1 */
> +#define MDSS_MDP_OP_DEINTERLACE            BIT(22)
> +#define MDSS_MDP_OP_DEINTERLACE_ODD        BIT(23)
> +#define MDSS_MDP_OP_IGC_ROM_1              BIT(18)
> +#define MDSS_MDP_OP_IGC_ROM_0              BIT(17)
> +#define MDSS_MDP_OP_IGC_EN                 BIT(16)
> +#define MDSS_MDP_OP_FLIP_UD                BIT(14)
> +#define MDSS_MDP_OP_FLIP_LR                BIT(13)
> +#define MDSS_MDP_OP_BWC_EN                 BIT(0)
> +#define MDSS_MDP_OP_PE_OVERRIDE            BIT(31)
> +#define MDSS_MDP_OP_BWC_LOSSLESS           (0 << 1)
> +#define MDSS_MDP_OP_BWC_Q_HIGH             (1 << 1)
> +#define MDSS_MDP_OP_BWC_Q_MED              (2 << 1)
>   
>   /* SSPP_QOS_CTRL */
>   #define SSPP_QOS_CTRL_VBLANK_EN            BIT(16)
> @@ -96,6 +91,7 @@
>   #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF      20
>   
>   /* DPU_SSPP_SCALER_QSEED2 */
> +#define SSPP_VIG_OP_MODE                   0x0
>   #define SCALE_CONFIG                       0x04
>   #define COMP0_3_PHASE_STEP_X               0x10
>   #define COMP0_3_PHASE_STEP_Y               0x14
> @@ -107,6 +103,9 @@
>   #define COMP1_2_INIT_PHASE_Y               0x2C
>   #define VIG_0_QSEED2_SHARP                 0x30
>   
> +/* SSPP_TRAFFIC_SHAPER and _REC1 */
> +#define SSPP_TRAFFIC_SHAPER_BPC_MAX        0xFF
> +
>   /*
>    * Definitions for ViG op modes
>    */
> @@ -128,6 +127,7 @@
>   /*
>    * Definitions for CSC 10 op modes
>    */
> +#define SSPP_VIG_CSC_10_OP_MODE            0x0
>   #define VIG_CSC_10_SRC_DATAFMT BIT(1)
>   #define VIG_CSC_10_EN          BIT(0)
>   #define CSC_10BIT_OFFSET       4