[PATCH 5/5] drm/i915: Include RPS threshold in error state

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Now that we allow them to be modified, lets include them in the error
state so it is visible when they have been modified in GPU hang triage.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi at kernel.org>
Cc: Andi Shyti <andi.shyti at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 5 +++++
 drivers/gpu/drm/i915/i915_gpu_error.h | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index ec368e700235..f9733c159b9b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -740,6 +740,8 @@ static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m,
 	err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake));
 	err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
 		   gt->clock_frequency, gt->clock_period_ns);
+	err_printf(m, "RPS thresholds up/down: %u/%u %%\n",
+		   gt->rps.up_threshold, gt->rps.down_threshold);
 	err_printf(m, "EIR: 0x%08x\n", gt->eir);
 	err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
 
@@ -2025,6 +2027,9 @@ intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
 	gc->_gt = gt;
 	gc->awake = intel_gt_pm_is_awake(gt);
 
+	gc->rps.up_threshold = gt->rps.power.up_threshold;
+	gc->rps.down_threshold = gt->rps.power.down_threshold;
+
 	gt_record_display_regs(gc);
 	gt_record_global_nonguc_regs(gc);
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index a78c061ce26f..6d2996ad2abb 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -140,6 +140,11 @@ struct intel_gt_coredump {
 	bool awake;
 	bool simulated;
 
+	struct {
+		u8 up_threshold;
+		u8 down_threshold;
+	} rps;
+
 	struct intel_gt_info info;
 
 	/* Generic register state */
-- 
2.39.2