[PATCH v9 RESEND 2/5] dt-bindings: display: Document Renesas RZ/G2L DU bindings

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Tue, May 02, 2023 at 11:09:09AM +0100, Biju Das wrote:
> The RZ/G2L LCD controller is composed of Frame Compression Processor
> (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
> 
> The DU module supports the following hardware features
> − Display Parallel Interface (DPI) and MIPI LINK Video Interface
> − Display timing master
> − Generates video timings
> − Selecting the polarity of output DCLK, HSYNC, VSYNC, and DE
> − Supports Progressive
> − Input data format (from VSPD): RGB888, RGB666
> − Output data format: same as Input data format
> − Supporting Full HD (1920 pixels x 1080 lines) for MIPI-DSI Output
> − Supporting WXGA (1280 pixels x 800 lines) for Parallel Output
> 
> This patch document DU module found on RZ/G2L LCDC.

s/document/documents the/

> Signed-off-by: Biju Das <biju.das.jz at bp.renesas.com>
> Reviewed-by: Rob Herring <robh at kernel.org>
> ---
> v8->v9:
>  * No change
> v7->v8:
>  * No change
> v6->v7:
>  * No change
> v5->v6:
>  * No change.
> v4->v5:
>  * Added Rb tag from Rob.
> v3->v4:
>  * Changed compatible name from renesas,du-r9a07g044->renesas,r9a07g044-du
>  * started using same compatible for RZ/G2{L,LC}
> v3: New patch
> ---
>  .../bindings/display/renesas,rzg2l-du.yaml    | 124 ++++++++++++++++++
>  1 file changed, 124 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> new file mode 100644
> index 000000000000..ab99e7d57a7d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> @@ -0,0 +1,124 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L Display Unit (DU)
> +
> +maintainers:
> +  - Biju Das <biju.das.jz at bp.renesas.com>
> +  - Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> +
> +description: |
> +  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
> +  and RZ/V2L SoCs.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - renesas,r9a07g044-du # RZ/G2{L,LC}
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Main clock
> +      - description: Register access clock
> +      - description: Video clock
> +
> +  clock-names:
> +    items:
> +      - const: aclk
> +      - const: pclk
> +      - const: vclk
> +
> +  resets:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +    description: |
> +      The connections to the DU output video ports are modeled using the OF
> +      graph bindings specified in Documentation/devicetree/bindings/graph.txt.

The file has moved to graph.yaml in the dt-schema repo. I'll drop the
last part of the sentence, starting with "specified by".

> +      The number of ports and their assignment are model-dependent. Each port
> +      shall have a single endpoint.
> +
> +    patternProperties:
> +      "^port@[0-1]$":
> +        $ref: /schemas/graph.yaml#/properties/port
> +        unevaluatedProperties: false
> +
> +    required:
> +      - port at 0
> +
> +    unevaluatedProperties: false
> +
> +  renesas,vsps:
> +    $ref: "/schemas/types.yaml#/definitions/phandle-array"
> +    items:
> +      items:
> +        - description: phandle to VSP instance that serves the DU channel
> +        - description: Channel index identifying the LIF instance in that VSP
> +    description:
> +      A list of phandle and channel index tuples to the VSPs that handle the
> +      memory interfaces for the DU channels.
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - resets
> +  - power-domains
> +  - ports
> +  - renesas,vsps
> +
> +additionalProperties: false
> +
> +examples:
> +  # RZ/G2L DU
> +  - |
> +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    display at 10890000 {
> +        compatible = "renesas,r9a07g044-du";
> +        reg = <0x10890000 0x10000>;
> +        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
> +                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
> +                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
> +        clock-names = "aclk", "pclk", "vclk";
> +        resets = <&cpg R9A07G044_LCDC_RESET_N>;
> +        power-domains = <&cpg>;
> +
> +        renesas,vsps = <&vspd0 0>;
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port at 0 {
> +                reg = <0>;
> +                endpoint {
> +                    remote-endpoint = <&dsi0_in>;
> +                };
> +            };
> +            port at 1 {
> +                reg = <1>;
> +                endpoint {
> +                };

Endpoints shouldn't be empty, you can just drop the endpoint here.

I'll fix all this locally.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

> +            };
> +        };
> +    };
> +
> +...

-- 
Regards,

Laurent Pinchart