[PATCH v2 07/11] drm/tidss: Add simple K2G manual reset
Tomi Valkeinen
tomi.valkeinen at ideasonboard.com
Thu Nov 9 07:38:00 UTC 2023
K2G display controller does not support soft reset, but we can do the
most important steps manually: mask the IRQs and disable the VPs.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index c82fd5bc9be4..a5c0b72596e8 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -2702,14 +2702,28 @@ static void dispc_init_errata(struct dispc_device *dispc)
}
}
+/*
+ * K2G display controller does not support soft reset, so we do a basic manual
+ * reset here: make sure the IRQs are masked and VPs are disabled.
+ */
+static void dispc_softreset_k2g(struct dispc_device *dispc)
+{
+ dispc_set_irqenable(dispc, 0);
+ dispc_read_and_clear_irqstatus(dispc);
+
+ for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx)
+ VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0);
+}
+
static int dispc_softreset(struct dispc_device *dispc)
{
u32 val;
int ret;
- /* K2G display controller does not support soft reset */
- if (dispc->feat->subrev == DISPC_K2G)
+ if (dispc->feat->subrev == DISPC_K2G) {
+ dispc_softreset_k2g(dispc);
return 0;
+ }
/* Soft reset */
REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
--
2.34.1
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