[PATCH v9 1/6] drm/panelreplay: dpcd register definition for panelreplay

[Manna, Animesh]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula at intel.com>
> Sent: Thursday, November 9, 2023 6:37 PM
> To: Manna, Animesh <animesh.manna at intel.com>; intel-
> gfx at lists.freedesktop.org; dri-devel at lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna at intel.com>; Hogander, Jouni
> <jouni.hogander at intel.com>; Murthy, Arun R <arun.r.murthy at intel.com>
> Subject: Re: [PATCH v9 1/6] drm/panelreplay: dpcd register definition for
> panelreplay
> 
> On Wed, 08 Nov 2023, Animesh Manna <animesh.manna at intel.com> wrote:
> > Add DPCD register definition for discovering, enabling and checking
> > status of panel replay of the sink.
> >
> > Cc: Jouni Högander <jouni.hogander at intel.com>
> > Cc: Arun R Murthy <arun.r.murthy at intel.com>
> > Cc: Jani Nikula <jani.nikula at intel.com>
> > Reviewed-by: Arun R Murthy <arun.r.murthy at intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna at intel.com>
> 
> You got the ack, please keep track of it.
> 
> https://lore.kernel.org/r/elcebygxs432bcj7oez7ndlfvb3lru7m7yznyqp2ei4ocjk
> vxp at 23lf2rh45fmt

Thanks Jani and everyone who helped in review.
Pushed the initial 5 patches of this series. As 6th patch has dependency on igt changes, will push after igt changes get merged.

Regards,
Animesh 
> 
> > ---
> >  include/drm/display/drm_dp.h | 23 +++++++++++++++++++++++
> >  1 file changed, 23 insertions(+)
> >
> > diff --git a/include/drm/display/drm_dp.h
> > b/include/drm/display/drm_dp.h index e69cece404b3..fc42b622ef32
> 100644
> > --- a/include/drm/display/drm_dp.h
> > +++ b/include/drm/display/drm_dp.h
> > @@ -543,6 +543,10 @@
> >  /* DFP Capability Extension */
> >  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
> >
> > +#define DP_PANEL_REPLAY_CAP                 0x0b0  /* DP 2.0 */
> > +# define DP_PANEL_REPLAY_SUPPORT            (1 << 0)
> > +# define DP_PANEL_REPLAY_SU_SUPPORT         (1 << 1)
> > +
> >  /* Link Configuration */
> >  #define	DP_LINK_BW_SET		            0x100
> >  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
> > @@ -716,6 +720,13 @@
> >  #define DP_BRANCH_DEVICE_CTRL		    0x1a1
> >  # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
> >
> > +#define PANEL_REPLAY_CONFIG                             0x1b0  /* DP 2.0 */
> > +# define DP_PANEL_REPLAY_ENABLE                         (1 << 0)
> > +# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN         (1 << 3)
> > +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN           (1 << 4)
> > +# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN      (1 << 5)
> > +# define DP_PANEL_REPLAY_SU_ENABLE                      (1 << 6)
> > +
> >  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
> >  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1  #define
> > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 @@ -1105,6 +1116,18
> @@
> >  #define DP_LANE_ALIGN_STATUS_UPDATED_ESI       0x200e /* status same
> as 0x204 */
> >  #define DP_SINK_STATUS_ESI                     0x200f /* status same as 0x205 */
> >
> > +#define DP_PANEL_REPLAY_ERROR_STATUS                   0x2020  /* DP 2.1*/
> > +# define DP_PANEL_REPLAY_LINK_CRC_ERROR                (1 << 0)
> > +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR             (1 << 1)
> > +# define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR   (1 << 2)
> > +
> > +#define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS        0x2022  /*
> DP 2.1 */
> > +# define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK       (7 << 0)
> > +# define DP_SINK_FRAME_LOCKED_SHIFT                    3
> > +# define DP_SINK_FRAME_LOCKED_MASK                     (3 << 3)
> > +# define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT       5
> > +# define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK        (1 << 5)
> > +
> >  /* Extended Receiver Capability: See DP_DPCD_REV for definitions */
> >  #define DP_DP13_DPCD_REV                    0x2200
> 
> --
> Jani Nikula, Intel