[3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values

[Sui Jingfeng]

Hi,


On 2023/9/13 14:06, Mitul Golani wrote:
> From: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while computing m_n values.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
>   drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>   drivers/gpu/drm/i915/display/intel_dp.c      | 5 +++--
>   drivers/gpu/drm/i915/display/intel_dp_mst.c  | 6 ++++--
>   drivers/gpu/drm/i915/display/intel_fdi.c     | 2 +-
>   5 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index afcbdd4f105a..b37aeac961f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2380,10 +2380,14 @@ void
>   intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
>   		       int pixel_clock, int link_clock,
>   		       struct intel_link_m_n *m_n,
> -		       bool fec_enable)
> +		       bool fec_enable,
> +		       bool is_dsc_fractional_bpp)
>   {
>   	u32 data_clock = bits_per_pixel * pixel_clock;
>   
> +	if (is_dsc_fractional_bpp)
> +		data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
> +

The 'bits_per_pixel * pixel_clock' has already been computed
and its result is stored in the 'data_clock' local variable.
can we change it as "data_clock = DIV_ROUND_UP(data_clock, 16)" here ?

>   	if (fec_enable)
>   		data_clock = intel_dp_mode_to_fec_clock(data_clock);
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 49ac8473b988..a4c4ca3cad65 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
>   void intel_link_compute_m_n(u16 bpp, int nlanes,
>   			    int pixel_clock, int link_clock,
>   			    struct intel_link_m_n *m_n,
> -			    bool fec_enable);
> +			    bool fec_enable, bool is_dsc_fractional_bpp);
>   u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>   			      u32 pixel_format, u64 modifier);
>   enum drm_mode_status
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index cb647bb38b12..6e09e21909a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2562,7 +2562,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
>   
>   	intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
>   			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
> -			       pipe_config->fec_enable);
> +			       pipe_config->fec_enable, false);
>   
>   	/* FIXME: abstract this better */
>   	if (pipe_config->splitter.enable)
> @@ -2741,7 +2741,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   			       adjusted_mode->crtc_clock,
>   			       pipe_config->port_clock,
>   			       &pipe_config->dp_m_n,
> -			       pipe_config->fec_enable);
> +			       pipe_config->fec_enable,
> +			       pipe_config->dsc.compression_enable);
>   
>   	/* FIXME: abstract this better */
>   	if (pipe_config->splitter.enable)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 7bf0b6e4ac0b..8f6bd54532cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -172,7 +172,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
>   			       adjusted_mode->crtc_clock,
>   			       crtc_state->port_clock,
>   			       &crtc_state->dp_m_n,
> -			       crtc_state->fec_enable);
> +			       crtc_state->fec_enable,
> +			       false);
>   	crtc_state->dp_m_n.tu = slots;
>   
>   	return 0;
> @@ -269,7 +270,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
>   			       adjusted_mode->crtc_clock,
>   			       crtc_state->port_clock,
>   			       &crtc_state->dp_m_n,
> -			       crtc_state->fec_enable);
> +			       crtc_state->fec_enable,
> +			       crtc_state->dsc.compression_enable);
>   	crtc_state->dp_m_n.tu = slots;
>   
>   	return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index e12b46a84fa1..15fddabf7c2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
>   	pipe_config->fdi_lanes = lane;
>   
>   	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> -			       link_bw, &pipe_config->fdi_m_n, false);
> +			       link_bw, &pipe_config->fdi_m_n, false, false);
>   
>   	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
>   	if (ret == -EDEADLK)