[PATCH] drm/msm: fix the highest_bank_bit for sc7180

[Abhinav Kumar]

On 8/12/2024 11:40 AM, Stephen Boyd wrote:
> Quoting Abhinav Kumar (2024-08-08 16:52:27)
>> sc7180 programs the ubwc settings as 0x1e as that would mean a
>> highest bank bit of 14 which matches what the GPU sets as well.
>>
>> However, the highest_bank_bit field of the msm_mdss_data which is
>> being used to program the SSPP's fetch configuration is programmed
>> to a highest bank bit of 16 as 0x3 translates to 16 and not 14.
>>
>> Fix the highest bank bit field used for the SSPP to match the mdss
>> and gpu settings.
>>
>> Fixes: 6f410b246209 ("drm/msm/mdss: populate missing data")
>> Signed-off-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
>> ---
>>   drivers/gpu/drm/msm/msm_mdss.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
>> index d90b9471ba6f..faa88fd6eb4d 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>> @@ -577,7 +577,7 @@ static const struct msm_mdss_data sc7180_data = {
>>          .ubwc_enc_version = UBWC_2_0,
>>          .ubwc_dec_version = UBWC_2_0,
>>          .ubwc_static = 0x1e,
>> -       .highest_bank_bit = 0x3,
>> +       .highest_bank_bit = 0x1,
> 
> Usually when I see hex it's because there's a mask. This isn't a mask
> though? Can it just be '1'?

I just retained the same convention that was used earlier. It seems like 
a mix and match right now. sc7180, sm6115 and qcm2290 were using 0x.

I can post a separate change to change all of them.