[PATCH] drm/v3d: Enable Performance Counters before clearing them

[Iago Toral]

Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>

El mié, 04-12-2024 a las 09:28 -0300, Maíra Canal escribió:
> On the Raspberry Pi 5, performance counters are not being cleared
> when `v3d_perfmon_start()` is called, even though we write to the
> CLR register. As a result, their values accumulate until they
> overflow.
> 
> The expected behavior is for performance counters to reset to zero
> at the start of a job. When the job finishes and the perfmon is
> stopped, the counters should accurately reflect the values for that
> specific job.
> 
> To ensure this behavior, the performance counters are now enabled
> before being cleared. This allows the CLR register to function as
> intended, zeroing the counter values when the job begins.
> 
> Fixes: 26a4dc29b74a ("drm/v3d: Expose performance counters to
> userspace")
> Signed-off-by: Maíra Canal <mcanal at igalia.com>
> ---
>  drivers/gpu/drm/v3d/v3d_perfmon.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/v3d/v3d_perfmon.c
> b/drivers/gpu/drm/v3d/v3d_perfmon.c
> index b4c3708ea781..c49abb90954d 100644
> --- a/drivers/gpu/drm/v3d/v3d_perfmon.c
> +++ b/drivers/gpu/drm/v3d/v3d_perfmon.c
> @@ -255,9 +255,9 @@ void v3d_perfmon_start(struct v3d_dev *v3d,
> struct v3d_perfmon *perfmon)
>  		V3D_CORE_WRITE(0, V3D_V4_PCTR_0_SRC_X(source),
> channel);
>  	}
>  
> +	V3D_CORE_WRITE(0, V3D_V4_PCTR_0_EN, mask);
>  	V3D_CORE_WRITE(0, V3D_V4_PCTR_0_CLR, mask);
>  	V3D_CORE_WRITE(0, V3D_PCTR_0_OVERFLOW, mask);
> -	V3D_CORE_WRITE(0, V3D_V4_PCTR_0_EN, mask);
>  
>  	v3d->active_perfmon = perfmon;
>  }