[PATCH 3/7] accel/qaic: Allocate an exact number of MSIs
Lizhi Hou
lizhi.hou at amd.com
Fri Dec 13 23:43:20 UTC 2024
On 12/13/24 13:33, Jeffrey Hugo wrote:
> From: Youssef Samir <quic_yabdulra at quicinc.com>
>
> Devices use 1 MSI vector for the MHI controller and as many vectors as
> the DMA bridge channels on the device. During the probing of the
> device, the driver allocates 32 MSI vectors, which is usually more
> than what is needed for AIC100 devices, which is wasting resources.
>
> Allocate only the needed number of MSI vectors per device.
>
> Signed-off-by: Youssef Samir <quic_yabdulra at quicinc.com>
> Reviewed-by: Troy Hanson <quic_thanson at quicinc.com>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
> Signed-off-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
> ---
> drivers/accel/qaic/qaic_drv.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c
> index 81819b9ef8d4..6e9bed17b3f1 100644
> --- a/drivers/accel/qaic/qaic_drv.c
> +++ b/drivers/accel/qaic/qaic_drv.c
> @@ -465,12 +465,13 @@ static int init_pci(struct qaic_device *qdev, struct pci_dev *pdev)
>
> static int init_msi(struct qaic_device *qdev, struct pci_dev *pdev)
> {
> + int irq_count = qdev->num_dbc + 1;
> int mhi_irq;
> int ret;
> int i;
>
> /* Managed release since we use pcim_enable_device */
> - ret = pci_alloc_irq_vectors(pdev, 32, 32, PCI_IRQ_MSI);
> + ret = pci_alloc_irq_vectors(pdev, irq_count, irq_count, PCI_IRQ_MSI);
> if (ret == -ENOSPC) {
> ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
> if (ret < 0)
> @@ -485,7 +486,8 @@ static int init_msi(struct qaic_device *qdev, struct pci_dev *pdev)
> * interrupted, it shouldn't race with itself.
> */
> qdev->single_msi = true;
> - pci_info(pdev, "Allocating 32 MSIs failed, operating in 1 MSI mode. Performance may be impacted.\n");
> + pci_info(pdev, "Allocating %d MSIs failed, operating in 1 MSI mode. Performance may be impacted.\n",
> + irq_count);
> } else if (ret < 0) {
> return ret;
> }
Reviewed-by: Lizhi Hou <lizhi.hou at amd.com>
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