[PATCH 7/7] accel/qaic: Add AIC200 support

[Lizhi Hou]

On 12/20/24 09:50, Jeffrey Hugo wrote:
> On 12/20/2024 10:33 AM, Lizhi Hou wrote:
>>
>> On 12/20/24 09:26, Jeffrey Hugo wrote:
>>> On 12/13/2024 5:49 PM, Lizhi Hou wrote:
>>>>
>>>> On 12/13/24 13:33, Jeffrey Hugo wrote:
>>>>> +static const struct qaic_device_config aic200_config = {
>>>>> +    .family = FAMILY_AIC200,
>>>>> +    .bar_mask = BIT(0) | BIT(1) | BIT(2) | BIT(4),
>>>>
>>>> Will this pass the BAR mask check in init_pci()?
>>>
>>> Yes, BITs 0, 1, 2, 4 would be 0x17 and that value is & with 0x3f 
>>> (masking off upper bits).  The result would be 0x17.
>>
>> It seems BIT(1) is not expected in init_pci?
>>
>>      if (bars != (BIT(0) | BIT(2) | BIT(4))) {
>
> I think you are only referencing patch 5, when you should also 
> reference patch 6.  This check gets modified in patch 6 -
>
> -    if (bars != (BIT(0) | BIT(2) | BIT(4))) {
> -        pci_dbg(pdev, "%s: expected BARs 0, 2, and 4 not found in 
> device. Found 0x%x\n",
> -            __func__, bars);
> +    if (bars != config->bar_mask) {
> +        pci_dbg(pdev, "%s: expected BARs %#x not found in device. 
> Found %#x\n",
> +            __func__, config->bar_mask, bars);
>          return -EINVAL;
>      }
>
>
> Do you still see an issue?
No. :)
Reviewed-by: Lizhi Hou <lizhi.hou at amd.com>