[PATCH v2] accel/ivpu: Don't enable any tiles by default on VPU40xx

[Jacek Lawrynowicz]

Applied to drm-misc-fixes

On 20.02.2024 14:16, Jacek Lawrynowicz wrote:
> From: Andrzej Kacprowski <Andrzej.Kacprowski at intel.com>
> 
> There is no point in requesting 1 tile on VPU40xx as the FW will
> probably need more tiles to run workloads, so it will have to
> reconfigure PLL anyway. Don't enable any tiles and allow the FW to
> perform initial tile configuration.
> 
> This improves NPU boot stability as the tiles are always enabled only
> by the FW from the same initial state.
> 
> Fixes: 79cdc56c4a54 ("accel/ivpu: Add initial support for VPU 4")
> Cc: stable at vger.kernel.org
> Signed-off-by: Andrzej Kacprowski <Andrzej.Kacprowski at intel.com>
> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz at linux.intel.com>
> ---
>  drivers/accel/ivpu/ivpu_hw_40xx.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/accel/ivpu/ivpu_hw_40xx.c b/drivers/accel/ivpu/ivpu_hw_40xx.c
> index 1c995307c113..a1523d0b1ef3 100644
> --- a/drivers/accel/ivpu/ivpu_hw_40xx.c
> +++ b/drivers/accel/ivpu/ivpu_hw_40xx.c
> @@ -24,7 +24,7 @@
>  #define SKU_HW_ID_SHIFT              16u
>  #define SKU_HW_ID_MASK               0xffff0000u
>  
> -#define PLL_CONFIG_DEFAULT           0x1
> +#define PLL_CONFIG_DEFAULT           0x0
>  #define PLL_CDYN_DEFAULT             0x80
>  #define PLL_EPP_DEFAULT              0x80
>  #define PLL_REF_CLK_FREQ	     (50 * 1000000)