[PATCH] drm/bridge: tc358767: Limit the Pixel PLL input range

[Lucas Stach]

Am Donnerstag, dem 18.01.2024 um 23:02 +0100 schrieb Marek Vasut:
> According to new configuration spreadsheet from Toshiba for TC9595,
> the Pixel PLL input clock have to be in range 6..40 MHz. The sheet
> calculates those PLL input clock as reference clock divided by both
> pre-dividers. Add the extra limit.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>

Reviewed-by: Lucas Stach <l.stach at pengutronix.de>

> ---
> Cc: Andrzej Hajda <andrzej.hajda at intel.com>
> Cc: Daniel Vetter <daniel at ffwll.ch>
> Cc: David Airlie <airlied at gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec at gmail.com>
> Cc: Jonas Karlman <jonas at kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart at ideasonboard.com>
> Cc: Lucas Stach <l.stach at pengutronix.de>
> Cc: Neil Armstrong <neil.armstrong at linaro.org>
> Cc: Robert Foss <rfoss at kernel.org>
> Cc: dri-devel at lists.freedesktop.org
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 615cc8f950d7b..0c29a8f81cc9e 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -546,9 +546,14 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
>  			continue;
>  		for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
>  			for (div = 1; div <= 16; div++) {
> -				u32 clk;
> +				u32 clk, iclk;
>  				u64 tmp;
>  
> +				/* PCLK PLL input unit clock ... 6..40 MHz */
> +				iclk = refclk / (div * ext_div[i_pre]);
> +				if (iclk < 6000000 || iclk > 40000000)
> +					continue;
> +
>  				tmp = pixelclock * ext_div[i_pre] *
>  				      ext_div[i_post] * div;
>  				do_div(tmp, refclk);