[PATCH 2/4] drm/bridge: add Microchip DSI controller support for sam9x7 SoC series

[Conor Dooley]

On Thu, Jul 11, 2024 at 11:05:37AM +0200, Krzysztof Kozlowski wrote:
> On 11/07/2024 10:30, Manikandan.M at microchip.com wrote:
> > Hi Krzysztof,
> > 
> > On 04/07/24 4:27 pm, Krzysztof Kozlowski wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On 04/07/2024 10:48, Manikandan Muralidharan wrote:
> >>> Add the Microchip's DSI controller wrapper driver that uses
> >>> the Synopsys DesignWare MIPI DSI host controller bridge.
> >>>
> >>> Signed-off-by: Manikandan Muralidharan <manikandan.m at microchip.com>
> >>> ---
> >>
> >>
> >> ...
> >>
> >>> +
> >>> +#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp)       \
> >>> +{                                    \
> >>> +     .maxfreq = _maxfreq,            \
> >>> +     .timing = {                     \
> >>> +             .clk_lp2hs = _c_lp2hs,  \
> >>> +             .clk_hs2lp = _c_hs2lp,  \
> >>> +             .data_lp2hs = _d_lp2hs, \
> >>> +             .data_hs2lp = _d_hs2lp, \
> >>> +     }                               \
> >>> +}
> >>> +
> >>> +struct hstt hstt_table[] = {
> >>
> >> So more globals? No.
> > 
> > In the sam9x7 datasheet, the high speed transition time for data and
> > clock lane at different freq for the DSI controller ranges are tabulated
> > with constant values.
> > I referred other similar platforms for the functionality and found 
> > similar way of implementation,  only a few had equations to derive the 
> > low power and high speed timings.I am not able to come up with a more 
> > efficient method. If there is something I am missing, please suggest.
> > TIA
> 
> Yeah, this should not be a global. Nothing above suggests it.

I think what Krzysztof is suggesting here is use of the static
keyword...

> 
> BTW, no W=1 clang warnings? Are you sure?
> 
> Best regards,
> Krzysztof
> 
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