[PATCH v2 8/9] arm64: dts: renesas: r9a07g043u: Add DU node

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Tue, Jul 09, 2024 at 02:51:46PM +0100, Biju Das wrote:
> Add DU node to RZ/G2UL SoC DTSI.
> 
> Signed-off-by: Biju Das <biju.das.jz at bp.renesas.com>
> ---
> v1->v2:
>  * No change.
> ---
>  arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 25 +++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> index d88bf23b0782..0a4f24d83791 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> @@ -153,6 +153,31 @@ fcpvd: fcp at 10880000 {
>  		resets = <&cpg R9A07G043_LCDC_RESET_N>;
>  	};
>  
> +	du: display at 10890000 {
> +		compatible = "renesas,r9a07g043u-du";
> +		reg = <0 0x10890000 0 0x10000>;
> +		interrupts = <SOC_PERIPHERAL_IRQ(152) IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
> +			 <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
> +			 <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
> +		clock-names = "aclk", "pclk", "vclk";
> +		power-domains = <&cpg>;
> +		resets = <&cpg R9A07G043_LCDC_RESET_N>;
> +		renesas,vsps = <&vspd 0>;
> +		status = "disabled";
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port at 1 {
> +				reg = <1>;

This may need to change depending on the outcome of the DT bindings
discussion. Other than that,

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>

> +				du_out_rgb: endpoint {
> +				};
> +			};
> +		};
> +	};
> +
>  	irqc: interrupt-controller at 110a0000 {
>  		compatible = "renesas,r9a07g043u-irqc",
>  			     "renesas,rzg2l-irqc";

-- 
Regards,

Laurent Pinchart