[PATCH 2/6] drm/bridge: tc358767: Use tc_pxl_pll_calc() to correct adjusted_mode clock

[Alexander Stein]

Hi Marek,

Am Freitag, 31. Mai 2024, 22:39:48 CEST schrieb Marek Vasut:
> Use tc_pxl_pll_calc() to find out the exact clock frequency generated by the
> Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency and
> pass it down the display pipeline to obtain exactly this frequency on input
> into this bridge.
> 
> The precise input frequency that matches the Pixel PLL frequency is
> important for this bridge, as if the frequencies do not match, the
> bridge does suffer VFIFO overruns or underruns.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> ---
> Cc: Andrzej Hajda <andrzej.hajda at intel.com>
> Cc: Daniel Vetter <daniel at ffwll.ch>
> Cc: David Airlie <airlied at gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec at gmail.com>
> Cc: Jonas Karlman <jonas at kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart at ideasonboard.com>
> Cc: Lucas Stach <l.stach at pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> Cc: Maxime Ripard <mripard at kernel.org>
> Cc: Neil Armstrong <neil.armstrong at linaro.org>
> Cc: Robert Foss <rfoss at kernel.org>
> Cc: Thomas Zimmermann <tzimmermann at suse.de>
> Cc: dri-devel at lists.freedesktop.org
> Cc: kernel at dh-electronics.com
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 45af31414ce48..252cc08dcc4a8 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -1619,6 +1619,18 @@ static int tc_dpi_atomic_check(struct drm_bridge *bridge,
>  			       struct drm_crtc_state *crtc_state,
>  			       struct drm_connector_state *conn_state)
>  {
> +	struct tc_data *tc = bridge_to_tc(bridge);
> +	int adjusted_clock = 0;
> +	int ret;
> +
> +	ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
> +			      crtc_state->adjusted_mode.clock * 1000,
> +			      &adjusted_clock, NULL);
> +	if (ret)
> +		return ret;
> +
> +	crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
> +
>  	/* DSI->DPI interface clock limitation: upto 100 MHz */
>  	if (crtc_state->adjusted_mode.clock > 100000)
>  		return -EINVAL;
> @@ -1631,6 +1643,18 @@ static int tc_edp_atomic_check(struct drm_bridge *bridge,
>  			       struct drm_crtc_state *crtc_state,
>  			       struct drm_connector_state *conn_state)
>  {
> +	struct tc_data *tc = bridge_to_tc(bridge);
> +	int adjusted_clock = 0;
> +	int ret;
> +
> +	ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
> +			      crtc_state->adjusted_mode.clock * 1000,
> +			      &adjusted_clock, NULL);
> +	if (ret)
> +		return ret;
> +
> +	crtc_state->adjusted_mode.clock = adjusted_clock / 1000;

This is prone to rounding errors. Debug output in my case:
> [   16.007127] tc358767 1-000f: enable video stream
> [   16.007148] tc358767 1-000f: PLL: requested 148500000 pixelclock, ref 26000000
> [   16.007163] tc358767 1-000f: PLL: got 147333333, delta -1166667
> [   16.007169] tc358767 1-000f: PLL: 26000000 / 1 / 1 * 17 / 3
> [   16.027112] tc358767 1-000f: set mode 1920x1080
> [   16.027138] tc358767 1-000f: H margin 148,88 sync 44
> [   16.027144] tc358767 1-000f: V margin 36,4 sync 5
> [   16.027150] tc358767 1-000f: total: 2200x1125
> [   16.059426] tc358767 1-000f: PLL: requested 147333000 pixelclock, ref 26000000
> [   16.059455] tc358767 1-000f: PLL: got 146250000, delta -1083000
> [   16.059461] tc358767 1-000f: PLL: 26000000 / 1 / 4 * 45 / 2
> [   16.095724] tc358767 1-000f: PLL: requested 146250000 pixelclock, ref 26000000
> [   16.095739] tc358767 1-000f: PLL: got 146250000, delta 0
> [   16.095745] tc358767 1-000f: PLL: 26000000 / 1 / 4 * 45 / 2

The accuracy degrades with each call, until a full kHz frequency is reached,
because drm_display_mode.clock only accounts for kHz, but the PLL
calculation takes Hz into account.

BTW: Which platform are you testing on?

Best regards,
Alexander

> +
>  	/* DPI->(e)DP interface clock limitation: upto 154 MHz */
>  	if (crtc_state->adjusted_mode.clock > 154000)
>  		return -EINVAL;
> 


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