[PATCH v5 2/3] dt-bindings: arm: mediatek: mmsys: Add OF graph support for board path

[CK Hu (胡俊光)]

Hi, Angelo:

On Tue, 2024-05-21 at 09:57 +0200, AngeloGioacchino Del Regno wrote:
> Document OF graph on MMSYS/VDOSYS: this supports up to three DDP paths
> per HW instance (so potentially up to six displays for multi-vdo SoCs).
> 
> The MMSYS or VDOSYS is always the first component in the DDP pipeline,
> so it only supports an output port with multiple endpoints - where each
> endpoint defines the starting point for one of the (currently three)
> possible hardware paths.
> 
> Reviewed-by: Rob Herring (Arm) <robh at kernel.org>
> Reviewed-by: Alexandre Mergnat <amergnat at baylibre.com>
> Tested-by: Alexandre Mergnat <amergnat at baylibre.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> ---
>  .../bindings/arm/mediatek/mediatek,mmsys.yaml | 28 +++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index b3c6888c1457..0ef67ca4122b 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -93,6 +93,34 @@ properties:
>    '#reset-cells':
>      const: 1
>  
> +  port:
> +    $ref: /schemas/graph.yaml#/properties/port
> +    description:
> +      Output port node. This port connects the MMSYS/VDOSYS output to
> +      the first component of one display pipeline, for example one of
> +      the available OVL or RDMA blocks.
> +      Some MediaTek SoCs support multiple display outputs per MMSYS.

This patch looks good to me. Just want to share another information for you.
Here is an example that mmsys/vdosys could point to the display interface node.

vdosys0: syscon at 1c01a000 {
          mmsys-display-interface = <&dsi0>, <&dsi1>, <&dp_intf0>;
};
 
vdosys1: syscon at 1c100000 {
          mmsys-display-interface = <&dp_intf1>;
};

There is no conflict that mmsys/vdosys point to first component of one display pipeline or point to display interface.
Both could co-exist.

Regards,
CK

> +    properties:
> +      endpoint at 0:
> +        $ref: /schemas/graph.yaml#/properties/endpoint
> +        description: Output to the primary display pipeline
> +
> +      endpoint at 1:
> +        $ref: /schemas/graph.yaml#/properties/endpoint
> +        description: Output to the secondary display pipeline
> +
> +      endpoint at 2:
> +        $ref: /schemas/graph.yaml#/properties/endpoint
> +        description: Output to the tertiary display pipeline
> +
> +    anyOf:
> +      - required:
> +          - endpoint at 0
> +      - required:
> +          - endpoint at 1
> +      - required:
> +          - endpoint at 2
> +
>  required:
>    - compatible
>    - reg
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