[PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for consistency

Wed Jun 5 12:49:40 UTC 2024

Hi,

I made a mistake while creating patch and this was sent by mistake. Please ignore this patch. I will rebase my patch series and send the correct version.

Sorry for inconvenience.

Regards,
Mitul

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Mitul
> Golani
> Sent: Wednesday, June 5, 2024 5:58 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: dri-devel at lists.freedesktop.org; Nautiyal, Ankit K
> <ankit.k.nautiyal at intel.com>; Nikula, Jani <jani.nikula at intel.com>
> Subject: [PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for
> consistency
> 
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> It's probably a good idea to start protecting all macro arguments to avoid any
> cargo-cult mistakes when people go looking for examples of how to define
> these things.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-
> 8-ville.syrjala at linux.intel.com
> Reviewed-by: Jani Nikula <jani.nikula at intel.com>
> ---
>  .../drm/i915/display/intel_pipe_crc_regs.h    | 26 +++++++++----------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
> b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
> index 383910a785f6..4e65f51d34e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
> @@ -9,7 +9,7 @@
>  #include "intel_display_reg_defs.h"
> 
>  #define _PIPE_CRC_CTL_A			0x60050
> -#define PIPE_CRC_CTL(dev_priv, pipe)		_MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_CTL_A)
> +#define PIPE_CRC_CTL(dev_priv, pipe)		_MMIO_TRANS2((dev_priv),
> (pipe), _PIPE_CRC_CTL_A)
>  #define   PIPE_CRC_ENABLE		REG_BIT(31)
>  /* skl+ source selection */
>  #define   PIPE_CRC_SOURCE_MASK_SKL	REG_GENMASK(30, 28)
> @@ -76,19 +76,19 @@
>  #define   PIPE_CRC_EXP_RES2_MASK	REG_BIT(22, 0) /* pre-ivb */
> 
>  #define _PIPE_CRC_RES_RED_A		0x60060
> -#define PIPE_CRC_RES_RED(dev_priv, pipe)	_MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_RED_A)
> +#define PIPE_CRC_RES_RED(dev_priv, pipe)	_MMIO_TRANS2((dev_priv),
> (pipe), _PIPE_CRC_RES_RED_A)
> 
>  #define _PIPE_CRC_RES_GREEN_A		0x60064
> -#define PIPE_CRC_RES_GREEN(dev_priv, pipe)	_MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_GREEN_A)
> +#define PIPE_CRC_RES_GREEN(dev_priv, pipe)	_MMIO_TRANS2((dev_priv),
> (pipe), _PIPE_CRC_RES_GREEN_A)
> 
>  #define _PIPE_CRC_RES_BLUE_A		0x60068
> -#define PIPE_CRC_RES_BLUE(dev_priv, pipe)	_MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_BLUE_A)
> +#define PIPE_CRC_RES_BLUE(dev_priv, pipe)	_MMIO_TRANS2((dev_priv),
> (pipe), _PIPE_CRC_RES_BLUE_A)
> 
>  #define _PIPE_CRC_RES_RES1_A_I915	0x6006c /* i915+ */
> -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe)
> 	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
> +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe)
> 	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915)
> 
>  #define _PIPE_CRC_RES_RES2_A_G4X	0x60080 /* g4x+ */
> -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)
> 	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
> +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)
> 	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X)
> 
>  /* ivb */
>  #define _PIPE_CRC_EXP_2_A_IVB		0x60054
> @@ -117,36 +117,36 @@
>  /* ivb */
>  #define _PIPE_CRC_RES_1_A_IVB		0x60064
>  #define _PIPE_CRC_RES_1_B_IVB		0x61064
> -#define PIPE_CRC_RES_1_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
> +#define PIPE_CRC_RES_1_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
> 
>  /* ivb */
>  #define _PIPE_CRC_RES_2_A_IVB		0x60068
>  #define _PIPE_CRC_RES_2_B_IVB		0x61068
> -#define PIPE_CRC_RES_2_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
> +#define PIPE_CRC_RES_2_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
> 
>  /* ivb */
>  #define _PIPE_CRC_RES_3_A_IVB		0x6006c
>  #define _PIPE_CRC_RES_3_B_IVB		0x6106c
> -#define PIPE_CRC_RES_3_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
> +#define PIPE_CRC_RES_3_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
> 
>  /* ivb */
>  #define _PIPE_CRC_RES_4_A_IVB		0x60070
>  #define _PIPE_CRC_RES_4_B_IVB		0x61070
> -#define PIPE_CRC_RES_4_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
> +#define PIPE_CRC_RES_4_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
> 
>  /* ivb */
>  #define _PIPE_CRC_RES_5_A_IVB		0x60074
>  #define _PIPE_CRC_RES_5_B_IVB		0x61074
> -#define PIPE_CRC_RES_5_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
> +#define PIPE_CRC_RES_5_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
> 
>  /* hsw+ */
>  #define _PIPE_CRC_EXP_A_HSW		0x60054
>  #define _PIPE_CRC_EXP_B_HSW		0x61054
> -#define PIPE_CRC_EXP_HSW(pipe)			_MMIO_PIPE(pipe,
> _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW)
> +#define PIPE_CRC_EXP_HSW(pipe)			_MMIO_PIPE((pipe),
> _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW)
> 
>  /* hsw+ */
>  #define _PIPE_CRC_RES_A_HSW		0x60064
>  #define _PIPE_CRC_RES_B_HSW		0x61064
> -#define PIPE_CRC_RES_HSW(pipe)			_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)
> +#define PIPE_CRC_RES_HSW(pipe)			_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)
> 
>  #endif /* __INTEL_PIPE_CRC_REGS_H__ */
> --
> 2.25.1