[PATCH v1] drm/bridge: it6505: update usleep_range for RC circuit charge time

[Robert Foss]

On Tue, 4 Jun 2024 10:44:05 +0800, kuro wrote:
> From: Kuro Chung <kuro.chung at ite.com.tw>
> 
> The spec of timing between IVDD/OVDD and SYSRTEN is 10ms, but SYSRSTN RC
> circuit need at least 25ms for rising time, update for match spec
> 
> 

Applied, thanks!

[1/1] drm/bridge: it6505: update usleep_range for RC circuit charge time
      https://cgit.freedesktop.org/drm/drm-misc/commit/?id=8814444e62b8



Rob