[PATCH v4 09/13] drm/msm/dpu: allow using two SSPP blocks for a single plane
Abhinav Kumar
quic_abhinavk at quicinc.com
Mon Jun 10 20:19:16 UTC 2024
On 3/13/2024 5:02 PM, Dmitry Baryshkov wrote:
> Virtual wide planes give high amount of flexibility, but it is not
> always enough:
>
> In parallel multirect case only the half of the usual width is supported
> for tiled formats. Thus the whole width of two tiled multirect
> rectangles can not be greater than max_linewidth, which is not enough
> for some platforms/compositors.
>
> Another example is as simple as wide YUV plane. YUV planes can not use
> multirect, so currently they are limited to max_linewidth too.
>
> Now that the planes are fully virtualized, add support for allocating
> two SSPP blocks to drive a single DRM plane. This fixes both mentioned
> cases and allows all planes to go up to 2*max_linewidth (at the cost of
> making some of the planes unavailable to the user).
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 172 ++++++++++++++++------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 8 +
> 2 files changed, 131 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 2961b809ccf3..cde20c1fa90d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -886,6 +886,28 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane,
> return 0;
> }
>
> +static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe *pipe,
> + struct dpu_sw_pipe_cfg *pipe_cfg,
> + const struct dpu_format *fmt,
> + uint32_t max_linewidth)
> +{
> + if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) ||
> + drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect))
> + return false;
> +
> + if (pipe_cfg->rotation & DRM_MODE_ROTATE_90)
> + return false;
> +
> + if (DPU_FORMAT_IS_YUV(fmt))
> + return false;
> +
> + if (DPU_FORMAT_IS_UBWC(fmt) &&
> + drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2)
> + return false;
> +
> + return true;
> +}
> +
This is a good idea to separate out multirect checks to a separate API.
I think can push this part of the change even today.
> static int dpu_plane_atomic_check_pipes(struct drm_plane *plane,
> struct drm_atomic_state *state,
> const struct drm_crtc_state *crtc_state)
> @@ -899,7 +921,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane,
> const struct dpu_format *fmt;
> struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
> struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
> - uint32_t max_linewidth;
> uint32_t supported_rotations;
> const struct dpu_sspp_cfg *pipe_hw_caps;
> const struct dpu_sspp_sub_blks *sblk;
> @@ -919,15 +940,8 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane,
> drm_rect_height(&new_plane_state->dst))))
> return -ERANGE;
>
> - pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> -
> fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
>
> - max_linewidth = pdpu->catalog->caps->max_linewidth;
> -
> supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
>
> if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION))
> @@ -943,41 +957,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane,
> return ret;
>
> if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
> - /*
> - * In parallel multirect case only the half of the usual width
> - * is supported for tiled formats. If we are here, we know that
> - * full width is more than max_linewidth, thus each rect is
> - * wider than allowed.
> - */
> - if (DPU_FORMAT_IS_UBWC(fmt) &&
> - drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
> - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n",
> - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
> - return -E2BIG;
> - }
> -
> - if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) ||
> - drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) ||
> - (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) &&
> - !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) ||
> - pipe_cfg->rotation & DRM_MODE_ROTATE_90 ||
> - DPU_FORMAT_IS_YUV(fmt)) {
> - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
> - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
> - return -E2BIG;
> - }
> -
> - /*
> - * Use multirect for wide plane. We do not support dynamic
> - * assignment of SSPPs, so we know the configuration.
> - */
> - pipe->multirect_index = DPU_SSPP_RECT_0;
> - pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
> -
> - r_pipe->sspp = pipe->sspp;
> - r_pipe->multirect_index = DPU_SSPP_RECT_1;
> - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
> -
> ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt,
> &crtc_state->adjusted_mode);
> if (ret)
> @@ -998,16 +977,16 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
> struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
> struct dpu_sw_pipe *pipe = &pstate->pipe;
> struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
> + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
> + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
> const struct drm_crtc_state *crtc_state = NULL;
>
> if (new_plane_state->crtc)
> crtc_state = drm_atomic_get_new_crtc_state(state,
> new_plane_state->crtc);
>
> - if (pdpu->pipe != SSPP_NONE) {
> - pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
> - r_pipe->sspp = NULL;
> - }
> + pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
> + r_pipe->sspp = NULL;
>
> if (!pipe->sspp)
> return -EINVAL;
> @@ -1019,6 +998,52 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
> if (!new_plane_state->visible)
> return 0;
>
> + pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> +
> + if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
> + uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth;
> + const struct dpu_format *fmt;
> +
> + fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
> +
> + /*
> + * In parallel multirect case only the half of the usual width
> + * is supported for tiled formats. If we are here, we know that
> + * full width is more than max_linewidth, thus each rect is
> + * wider than allowed.
> + */
> + if (DPU_FORMAT_IS_UBWC(fmt) &&
> + drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
> + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n",
> + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
> + return -E2BIG;
> + }
> +
> + r_pipe->sspp = pipe->sspp;
> +
> + if (!dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_linewidth) ||
> + !dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max_linewidth) ||
> + !(test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) ||
> + test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) {
> + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
> + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
> + return -E2BIG;
> + }
> +
> + /*
> + * Use multirect for wide plane. We do not support dynamic
> + * assignment of SSPPs, so we know the configuration.
> + */
> + pipe->multirect_index = DPU_SSPP_RECT_0;
> + pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
> +
> + r_pipe->multirect_index = DPU_SSPP_RECT_1;
> + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
> + }
> +
I might be wrong here, but it seems like this part was moved to
dpu_plane_atomic_check_nopipe() in patch 6 and now being brought back
(atleast most of it) to dpu_plane_atomic_check().
If this is correct, then the migration in patch 6 was not necessary.
> return dpu_plane_atomic_check_pipes(plane, state, crtc_state);
> }
>
> @@ -1053,10 +1078,18 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
>
> format = to_dpu_format(msm_framebuffer_format(plane_state->fb));
>
> - /* force resource reallocation if the format of FB has changed */
> - if (pstate->saved_fmt != format) {
> + /* force resource reallocation if the format of FB or src/dst have changed */
> + if (pstate->saved_fmt != format ||
> + pstate->saved_src_w != plane_state->src_w ||
> + pstate->saved_src_h != plane_state->src_h ||
> + pstate->saved_src_w != plane_state->src_w ||
> + pstate->saved_crtc_h != plane_state->crtc_h) {
> crtc_state->planes_changed = true;
> pstate->saved_fmt = format;
> + pstate->saved_src_w = plane_state->src_w;
> + pstate->saved_src_h = plane_state->src_h;
> + pstate->saved_crtc_w = plane_state->crtc_w;
> + pstate->saved_crtc_h = plane_state->crtc_h;
> }
Is thic chunk checking that if the src/dst have changed, this plane
might span more than one LM?
Will be better to add more comment on why we are also checking src/dest
changes.
Overall, can we just use for_each_oldnew_plane_in_state to compare the
prev and current dimensions and drop saved_****?
>
> return 0;
> @@ -1074,7 +1107,10 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
> struct dpu_plane_state *pstate;
> struct dpu_sw_pipe *pipe;
> struct dpu_sw_pipe *r_pipe;
> + struct dpu_sw_pipe_cfg *pipe_cfg;
> + struct dpu_sw_pipe_cfg *r_pipe_cfg;
> const struct dpu_format *fmt;
> + uint32_t max_linewidth;
>
> if (plane_state->crtc)
> crtc_state = drm_atomic_get_new_crtc_state(state,
> @@ -1083,6 +1119,8 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
> pstate = to_dpu_plane_state(plane_state);
> pipe = &pstate->pipe;
> r_pipe = &pstate->r_pipe;
> + pipe_cfg = &pstate->pipe_cfg;
> + r_pipe_cfg = &pstate->r_pipe_cfg;
>
> pipe->sspp = NULL;
> r_pipe->sspp = NULL;
> @@ -1097,10 +1135,46 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
>
> reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation);
>
> + max_linewidth = dpu_kms->catalog->caps->max_linewidth;
> +
> pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
> if (!pipe->sspp)
> return -ENODEV;
>
> + if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) {
> + pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> +
> + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> +
> + r_pipe->sspp = NULL;
> + } else {
> + if (dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_linewidth) &&
> + dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max_linewidth) &&
> + (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) ||
> + test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) {
> + r_pipe->sspp = pipe->sspp;
> +
> + pipe->multirect_index = DPU_SSPP_RECT_0;
> + pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
> +
> + r_pipe->multirect_index = DPU_SSPP_RECT_1;
> + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
> + } else {
> + /* multirect is not possible, use two SSPP blocks */
> + r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
> + if (!r_pipe->sspp)
> + return -ENODEV;
> +
> + pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> +
> + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> + }
> + }
> +
This chunk LGTM.
> return dpu_plane_atomic_check_pipes(plane, state, crtc_state);
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index 15f7d60d8b85..5522f9035d68 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -31,6 +31,10 @@
> * @plane_clk: calculated clk per plane
> * @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed
> * @saved_fmt: format used by the plane's FB, saved for for virtual plane support
> + * @saved_src_w: cached value of plane's src_w, saved for for virtual plane support
> + * @saved_src_h: cached value of plane's src_h, saved for for virtual plane support
> + * @saved_crtc_w: cached value of plane's crtc_w, saved for for virtual plane support
> + * @saved_crtc_h: cached value of plane's crtc_h, saved for for virtual plane support
> */
> struct dpu_plane_state {
> struct drm_plane_state base;
> @@ -49,6 +53,10 @@ struct dpu_plane_state {
> bool needs_dirtyfb;
>
> const struct dpu_format *saved_fmt;
> + uint32_t saved_src_w;
> + uint32_t saved_src_h;
> + uint32_t saved_crtc_w;
> + uint32_t saved_crtc_h;
> };
>
> #define to_dpu_plane_state(x) \
More information about the dri-devel
mailing list