[PATCH 4/9] arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588s

[Diederik de Haas]

Hi,

On Wednesday, 12 June 2024 15:52:57 CEST Tomeu Vizoso wrote:
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 53
> +++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index
> 6ac5ac8b48ab..a5d53578c8f6 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -2665,6 +2665,59 @@ gpio4: gpio at fec50000 {
>                         #interrupt-cells = <2>;
>                 };
>         };
> +
> +       rknn: npu at fdab0000 {
> +               compatible = "rockchip,rk3588-rknn", "rockchip,rknn";
> +               reg = <0x0 0xfdab0000 0x0 0x9000>,
> +                     <0x0 0xfdac0000 0x0 0x9000>,
> +                     <0x0 0xfdad0000 0x0 0x9000>;
> +               interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
> +                            <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
> +                            <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
> +               interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq";
> +               clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>,
> +                        <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
> +                        <&cru HCLK_NPU0>, <&cru HCLK_NPU1>,
> +                        <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>;
> +               clock-names = "clk_npu",
> +                             "aclk0", "aclk1", "aclk2",
> +                             "hclk0", "hclk1", "hclk2",
> +                             "pclk";
> +               assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
> +               assigned-clock-rates = <200000000>;
> +               resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru
> SRST_A_RKNN2>, +                        <&cru SRST_H_RKNN0>, <&cru
> SRST_H_RKNN1>, <&cru SRST_H_RKNN2>; +               reset-names =
> "srst_a0", "srst_a1", "srst_a2",
> +                             "srst_h0", "srst_h1", "srst_h2";
> +               power-domains = <&power RK3588_PD_NPUTOP>,
> +                               <&power RK3588_PD_NPU1>,
> +                               <&power RK3588_PD_NPU2>;
> +               power-domain-names = "npu0", "npu1", "npu2";
> +               iommus = <&rknn_mmu>;
> +               status = "disabled";
> +       };
> +
> +       rknn_mmu: iommu at fdab9000 {
> +               compatible = "rockchip,rk3588-iommu";
> +               reg = <0x0 0xfdab9000 0x0 0x100>,
> +                     <0x0 0xfdaba000 0x0 0x100>,
> +                     <0x0 0xfdaca000 0x0 0x100>,
> +                     <0x0 0xfdada000 0x0 0x100>;
> +               interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
> +                            <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
> +                            <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
> +               interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu";
> +               clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru
> ACLK_NPU2>, +                        <&cru HCLK_NPU0>, <&cru HCLK_NPU1>,
> <&cru HCLK_NPU2>; +               clock-names = "aclk0", "aclk1", "aclk2",
> +                             "iface0", "iface1", "iface2";
> +               #iommu-cells = <0>;
> +               power-domains = <&power RK3588_PD_NPUTOP>,
> +                               <&power RK3588_PD_NPU1>,
> +                               <&power RK3588_PD_NPU2>;
> +               power-domain-names = "npu0", "npu1", "npu2";
> +               status = "disabled";
> +       };

The nodes should be sorted by address, so these nodes should come between
pmu: power-management at fd8d8000 {
and 
av1d: video-codec at fdc70000 {

Cheers,
  Diederik
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