[PATCH v4 4/4] arm64: dts: qcom: add HDMI nodes for msm8998
Marc Gonzalez
mgonzalez at freebox.fr
Thu Jun 13 15:15:53 UTC 2024
From: Arnaud Vrac <avrac at freebox.fr>
Port device nodes from vendor code.
Signed-off-by: Arnaud Vrac <avrac at freebox.fr>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
Signed-off-by: Marc Gonzalez <mgonzalez at freebox.fr>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 100 +++++++++++++++++++++++++++++++++-
1 file changed, 99 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index ba5e873f0f35f..5c53957da61c5 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -2785,7 +2785,7 @@ mmcc: clock-controller at c8c0000 {
<&mdss_dsi0_phy 0>,
<&mdss_dsi1_phy 1>,
<&mdss_dsi1_phy 0>,
- <0>,
+ <&hdmi_phy 0>,
<0>,
<0>,
<&gcc GCC_MMSS_GPLL0_DIV_CLK>;
@@ -2890,6 +2890,14 @@ dpu_intf2_out: endpoint {
remote-endpoint = <&mdss_dsi1_in>;
};
};
+
+ port at 2 {
+ reg = <2>;
+
+ dpu_intf3_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
};
};
@@ -3045,6 +3053,96 @@ mdss_dsi1_phy: phy at c996400 {
status = "disabled";
};
+
+ hdmi: hdmi-tx at c9a0000 {
+ compatible = "qcom,hdmi-tx-8998";
+ reg = <0x0c9a0000 0x50c>,
+ <0x00780000 0x6220>,
+ <0x0c9e0000 0x2c>;
+ reg-names = "core_physical",
+ "qfprom_physical",
+ "hdcp_physical";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <8>;
+
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_HDMI_CLK>,
+ <&mmcc MDSS_HDMI_DP_AHB_CLK>,
+ <&mmcc MDSS_EXTPCLK_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MNOC_AHB_CLK>,
+ <&mmcc MISC_AHB_CLK>;
+ clock-names =
+ "mdp_core",
+ "iface",
+ "core",
+ "alt_iface",
+ "extp",
+ "bus",
+ "mnoc",
+ "iface_mmss";
+
+ phys = <&hdmi_phy>;
+ #sound-dai-cells = <1>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hdmi_hpd_default
+ &hdmi_ddc_default
+ &hdmi_cec_default>;
+ pinctrl-1 = <&hdmi_hpd_sleep
+ &hdmi_ddc_default
+ &hdmi_cec_default>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ hdmi_in: endpoint {
+ remote-endpoint = <&dpu_intf3_out>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ hdmi_out: endpoint {
+ };
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy at c9a0600 {
+ compatible = "qcom,hdmi-phy-8998";
+ reg = <0x0c9a0600 0x18b>,
+ <0x0c9a0a00 0x38>,
+ <0x0c9a0c00 0x38>,
+ <0x0c9a0e00 0x38>,
+ <0x0c9a1000 0x38>,
+ <0x0c9a1200 0x0e8>;
+ reg-names = "hdmi_pll",
+ "hdmi_tx_l0",
+ "hdmi_tx_l1",
+ "hdmi_tx_l2",
+ "hdmi_tx_l3",
+ "hdmi_phy";
+
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&gcc GCC_HDMI_CLKREF_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface",
+ "ref",
+ "xo";
+
+ status = "disabled";
+ };
};
venus: video-codec at cc00000 {
--
2.34.1
More information about the dri-devel
mailing list