[PATCH V2] drm/ttm: increase ttm pre-fault value to PMD size

Christian König christian.koenig at amd.com
Thu Jun 20 14:01:00 UTC 2024


Am 19.06.24 um 18:09 schrieb Alex Deucher:
> On Tue, Jun 4, 2024 at 10:02 AM Christian König
> <christian.koenig at amd.com> wrote:
>> Am 04.06.24 um 12:18 schrieb Huang Rui:
>>> On Tue, Jun 04, 2024 at 04:49:34PM +0800, Zhu, Lingshan wrote:
>>>> ttm page fault handler ttm_bo_vm_fault_reserved() maps
>>>> TTM_BO_VM_NUM_PREFAULT more pages beforehand
>>>> due to the principle of locality.
>>>>
>>>> However, on some platform the page faults are more costly, this
>>>> patch intends to increase the number of ttm pre-fault to relieve
>>>> the number of page faults.
>>>>
>>>> When multiple levels of page table is supported, the new default
>>>> value would be the PMD size, similar to huge page.
>>>>
>>>> Signed-off-by: Zhu Lingshan <lingshan.zhu at amd.com>
>>>> Reported-and-tested-by: Li Jingxiang <jingxiang.li at ecarxgroup.com>
>>> Acked-by: Huang Rui <ray.huang at amd.com>
>> Not sure if there really is an architecture with less than 3 page table
>> levels, but the build robots should be able to tell us if everything is
>> fine here.
>>
>> Reviewed-by: Christian König <christian.koenig at amd.com>
> Has this been pushed to drm-misc?  If not, can you push it?

Done.

Christian.

>
> Thanks,
>
> Alex
>
>>>> ---
>>>>    include/drm/ttm/ttm_bo.h | 4 ++++
>>>>    1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h
>>>> index 6ccf96c91f3a..ef0f52f56ebc 100644
>>>> --- a/include/drm/ttm/ttm_bo.h
>>>> +++ b/include/drm/ttm/ttm_bo.h
>>>> @@ -39,7 +39,11 @@
>>>>    #include "ttm_device.h"
>>>>
>>>>    /* Default number of pre-faulted pages in the TTM fault handler */
>>>> +#if CONFIG_PGTABLE_LEVELS > 2
>>>> +#define TTM_BO_VM_NUM_PREFAULT (1 << (PMD_SHIFT - PAGE_SHIFT))
>>>> +#else
>>>>    #define TTM_BO_VM_NUM_PREFAULT 16
>>>> +#endif
>>>>
>>>>    struct iosys_map;
>>>>
>>>> --
>>>> 2.45.1
>>>>



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