[PATCH 4/4] drm: rcar-du: Add support for R8A779H0

[Jacopo Mondi]

Hi Geert

On Thu, Jun 20, 2024 at 02:48:49PM GMT, Geert Uytterhoeven wrote:
> Hi Laurent, Jacopo,
>
> On Wed, Jun 19, 2024 at 9:46 PM Laurent Pinchart
> <laurent.pinchart at ideasonboard.com> wrote:
> > On Wed, Jun 19, 2024 at 12:22:18PM +0200, Jacopo Mondi wrote:
> > > Add support for R-Car R8A779H0 V4M which has similar characteristics
> > > as the already supported R-Car V4H R8A779G0, but with a single output
> > > channel.
> > >
> > > Signed-off-by: Jacopo Mondi <jacopo.mondi at ideasonboard.com>
>
> > > --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c
> > > +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c
> > > @@ -185,11 +187,16 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
> > >               dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1;
> > >       rcar_du_group_write(rgrp, DORCR, dorcr);
> > >
> > > -     /* Apply planes to CRTCs association. */
> > > -     mutex_lock(&rgrp->lock);
> > > -     rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
> > > -                         rgrp->dptsr_planes);
> > > -     mutex_unlock(&rgrp->lock);
> > > +     /*
> > > +      * Apply planes to CRTCs association, skip for V4M which has a single
> > > +      * channel.
> >
> > " and doesn't implement the DPTSR register."
> >
> > I'm pretty sure writing it is still harmless, but...
> >
> > > +      */
> > > +     if (rcdu->info->gen < 4 || rgrp->num_crtcs > 1) {
>
> Looking at the R-Car Gen3 docs, this check seems to be wrong, and the
> lack of a check might have been an issue before?


Not sure I got from your comment what part is wrong.

Reading below it seems you're suggesting that writes to DPTSR should
be skipped for some Gen3 boards as well ?

>
> Seems like the register (per pair) is only present if the second CRTC
> of a CRTC pair is present, so R-Car V3M and V3H (single CRTC) do not
> have DPTSR at all, and M3-W (triple CRTC) does not have it on the
> second pair.  M3-N does have both, as it lacks the first CRTC of
> second pair, but does have the second CRTC of the second pair.
>

/o\

So far however, all Gen3 SoCs you mentioned seem to work with DPTSR
being written and the BSP [1] only actually skips it for V4M.

What would you suggesting in this case ? Addressing gen3 as well ?
That's something that would require testing on all the above boards
thought.

Thanks
  j


[1] https://github.com/renesas-rcar/linux-bsp/commit/f2fc3314dab2052240653c1a31ba3d7c7190038e#diff-8bce6f4032dc891042e2561163754f49723ac119ae63df2425cc3487b432ee1cR206
> > > +             mutex_lock(&rgrp->lock);
> > > +             rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
> > > +                                 rgrp->dptsr_planes);
> > > +             mutex_unlock(&rgrp->lock);
> > > +     }
> > >  }
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds