[PATCH 3/3] dt-bindings: display/msm/gpu: constrain reg/reg-names per variant

[Conor Dooley]

On Sun, Jun 23, 2024 at 02:00:26PM +0200, Krzysztof Kozlowski wrote:
> MMIO address space is known per each variant of Adreno GPU, so we can
> constrain the reg/reg-names entries for each variant.  There is no DTS
> for A619, so that part is not accurate but could be corrected later.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> ---
>  .../devicetree/bindings/display/msm/gpu.yaml  | 87 +++++++++++++++++--
>  1 file changed, 79 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> index baea1946c65d..e83f13123fc9 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> @@ -130,6 +130,22 @@ required:
>  additionalProperties: false
>  
>  allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'

Does the regex "^qcom,adreno-[0-9a-f]{8}$" not work in dt-schema, rather
than this repeat-a-number-of-times-I-cannot-grok that's happening here?
(I know you probably just copied this from above in the file...)
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