[PATCH v3 6/6] Revert "drm/bridge: tc358767: Set default CLRSIPO count"

[Alexander Stein]

Am Sonntag, 23. Juni 2024, 16:38:38 CEST schrieb Marek Vasut:
> This reverts commit 01338bb82fed40a6a234c2b36a92367c8671adf0.
> 
> With clock improvements in place, this seems to be no longer
> necessary. Set the CLRSIPO to default setting recommended by
> manufacturer.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>

Although calculation sheet indicates this depends on DSI-Timings, this
works as well.
Reviewed-by: Alexander Stein <alexander.stein at ew.tq-group.com>

> ---
> Cc: Andrzej Hajda <andrzej.hajda at intel.com>
> Cc: Daniel Vetter <daniel at ffwll.ch>
> Cc: David Airlie <airlied at gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec at gmail.com>
> Cc: Jonas Karlman <jonas at kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart at ideasonboard.com>
> Cc: Lucas Stach <l.stach at pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> Cc: Maxime Ripard <mripard at kernel.org>
> Cc: Neil Armstrong <neil.armstrong at linaro.org>
> Cc: Robert Foss <rfoss at kernel.org>
> Cc: Thomas Zimmermann <tzimmermann at suse.de>
> Cc: dri-devel at lists.freedesktop.org
> Cc: kernel at dh-electronics.com
> ---
> V2: No change
> V3: No change
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 743bf1334923d..2b035a136a6e5 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -1356,10 +1356,10 @@ static int tc_dsi_rx_enable(struct tc_data *tc)
>  	u32 value;
>  	int ret;
>  
> -	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
> -	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
> -	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
> -	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
> +	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
> +	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
> +	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
> +	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
>  	regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
>  	regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
>  	regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
> 


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