[PATCH v15 8/9] drm/i915/display: Compute vrr_vsync params
Nautiyal, Ankit K
ankit.k.nautiyal at intel.com
Mon Mar 4 10:52:54 UTC 2024
On 3/1/2024 2:15 PM, Mitul Golani wrote:
> Compute vrr_vsync_start/end, which sets the position
> for hardware to send the Vsync at a fixed position
> relative to the end of the Vblank.
>
> --v2:
> - Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
> - Updated bit fields of VRR_VSYNC_START/END. (Ankit)
>
> --v3:
> - Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
> - Read/write vrr_vsync params only when we intend to send
> adaptive_sync sdp.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 29 +++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++
> 4 files changed, 37 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 88158f06bf82..f62c3ae7f0fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5377,6 +5377,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(vrr.flipline);
> PIPE_CONF_CHECK_I(vrr.pipeline_full);
> PIPE_CONF_CHECK_I(vrr.guardband);
> + PIPE_CONF_CHECK_I(vrr.vsync_start);
> + PIPE_CONF_CHECK_I(vrr.vsync_end);
> }
>
> #undef PIPE_CONF_CHECK_X
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 098957cea25b..e8ba3c077569 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1423,6 +1423,7 @@ struct intel_crtc_state {
> bool enable, in_range;
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> + u32 vsync_end, vsync_start;
> } vrr;
>
> /* Stream Splitter for eDP MSO */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5d905f932cb4..d24a42902e69 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -9,6 +9,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_vrr.h"
> +#include "intel_dp.h"
>
> bool intel_vrr_is_capable(struct intel_connector *connector)
> {
> @@ -113,6 +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> + struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> const struct drm_display_info *info = &connector->base.display_info;
> int vmin, vmax;
> @@ -165,6 +167,15 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> if (crtc_state->uapi.vrr_enabled) {
> crtc_state->vrr.enable = true;
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> +
> + if (intel_dp_as_sdp_supported(intel_dp)) {
> + crtc_state->vrr.vsync_start =
> + (crtc_state->hw.adjusted_mode.crtc_vtotal -
> + VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start));
> + crtc_state->vrr.vsync_end =
> + (crtc_state->hw.adjusted_mode.crtc_vtotal -
> + (VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16));
I think you are using the VRR_SYNC_START/END macros incorrectly.
We dont need to use these macros here.
> + }
> }
> }
>
> @@ -203,6 +214,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
> intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
> intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
> +
> + if (crtc_state->vrr.vsync_end && crtc_state->vrr.vsync_start)
> + intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
> + crtc_state->vrr.vsync_end << 16 | crtc_state->vrr.vsync_start);
Here is where the macros should be used.
VRR_SYNC_END(crtc_state->vrr.vsync_end) |
VRR_SYNC_START(crtc_state->vrr.vsync_start);
> }
>
> void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
> @@ -263,7 +278,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - u32 trans_vrr_ctl;
> + u32 trans_vrr_ctl, trans_vrr_vsync;
>
> trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
>
> @@ -283,6 +298,16 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
> }
>
> - if (crtc_state->vrr.enable)
> + if (crtc_state->vrr.enable) {
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> +
> + if (HAS_AS_SDP(dev_priv)) {
> + trans_vrr_vsync =
> + intel_de_read(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder));
> + crtc_state->vrr.vsync_start =
> + trans_vrr_vsync & VRR_VSYNC_START_MASK;
> + crtc_state->vrr.vsync_end =
> + trans_vrr_vsync & VRR_VSYNC_START_MASK;
Here too you should use REG_FIELD_GET(VRR_VSYNC_START/END_MASK,
trans_vrr_vsync) to fill crtc_state->vrr.sync_start/end.
Regards,
Ankit
> + }
> + }
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dce276236707..53d8eb7ea1ea 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2007,7 +2007,9 @@
> #define _TRANS_VRR_CTL_B 0x61420
> #define _TRANS_VRR_CTL_C 0x62420
> #define _TRANS_VRR_CTL_D 0x63420
> +#define _TRANS_VRR_VSYNC_A 0x60078
> #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
> +#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A)
> #define VRR_CTL_VRR_ENABLE REG_BIT(31)
> #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> @@ -2087,6 +2089,11 @@
> #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
> #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
>
> +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
> +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
> +
> #define _TRANS_PUSH_A 0x60A70
> #define _TRANS_PUSH_B 0x61A70
> #define _TRANS_PUSH_C 0x62A70
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