[drm-misc:drm-misc-next 7/10] drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:122:25: sparse: sparse: incorrect type in argument 1 (different address spaces)
kernel test robot
lkp at intel.com
Mon May 27 23:27:01 UTC 2024
tree: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
head: 40f98db5c06081ce583a24fb8950367f1058d2a3
commit: dc6fcaaba5a5411237d042a26c4d46689f3346bb [7/10] drm/omap: Allow build with COMPILE_TEST=y
config: mips-randconfig-r133-20240528 (https://download.01.org/0day-ci/archive/20240528/202405280709.9vMmDoGt-lkp@intel.com/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce: (https://download.01.org/0day-ci/archive/20240528/202405280709.9vMmDoGt-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405280709.9vMmDoGt-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:122:25: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned int [usertype] *wa_dma_data @@
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:122:25: sparse: expected void const volatile [noderef] __iomem *mem
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:122:25: sparse: got unsigned int [usertype] *wa_dma_data
>> drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:130:24: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned int [usertype] *wa_dma_data @@
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:130:24: sparse: expected void volatile [noderef] __iomem *mem
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:130:24: sparse: got unsigned int [usertype] *wa_dma_data
>> drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:414:19: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned int * @@
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:414:19: sparse: expected void const volatile [noderef] __iomem *mem
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c:414:19: sparse: got unsigned int *
vim +122 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 101
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 102 static u32 dmm_read_wa(struct dmm *dmm, u32 reg)
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 103 {
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 104 dma_addr_t src, dst;
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 105 int r;
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 106
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 107 src = dmm->phys_base + reg;
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 108 dst = dmm->wa_dma_handle;
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 109
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 110 r = dmm_dma_copy(dmm, src, dst);
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 111 if (r) {
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 112 dev_err(dmm->dev, "sDMA read transfer timeout\n");
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 113 return readl(dmm->base + reg);
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 114 }
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 115
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 116 /*
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 117 * As per i878 workaround, the DMA is used to access the DMM registers.
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 118 * Make sure that the readl is not moved by the compiler or the CPU
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 119 * earlier than the DMA finished writing the value to memory.
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 120 */
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 121 rmb();
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 @122 return readl(dmm->wa_dma_data);
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 123 }
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 124
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 125 static void dmm_write_wa(struct dmm *dmm, u32 val, u32 reg)
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 126 {
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 127 dma_addr_t src, dst;
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 128 int r;
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 129
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 @130 writel(val, dmm->wa_dma_data);
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 131 /*
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 132 * As per i878 workaround, the DMA is used to access the DMM registers.
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 133 * Make sure that the writel is not moved by the compiler or the CPU, so
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 134 * the data will be in place before we start the DMA to do the actual
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 135 * register write.
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 136 */
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 137 wmb();
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 138
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 139 src = dmm->wa_dma_handle;
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 140 dst = dmm->phys_base + reg;
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 141
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 142 r = dmm_dma_copy(dmm, src, dst);
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 143 if (r) {
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 144 dev_err(dmm->dev, "sDMA write transfer timeout\n");
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 145 writel(val, dmm->base + reg);
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 146 }
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 147 }
f5b9930b85dc631 Tomi Valkeinen 2018-09-26 148
:::::: The code at line 122 was first introduced by commit
:::::: f5b9930b85dc6319fd6bcc259e447eff62fc691c drm/omap: partial workaround for DRA7xx DMM errata i878
:::::: TO: Tomi Valkeinen <tomi.valkeinen at ti.com>
:::::: CC: Tomi Valkeinen <tomi.valkeinen at ti.com>
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