[PATCHv2 1/8] drm/i915/histogram: Define registers for histogram

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Arun R
> Murthy
> Sent: Tuesday, November 19, 2024 4:15 PM
> To: intel-xe at lists.freedesktop.org; intel-gfx at lists.freedesktop.org; dri-
> devel at lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy at intel.com>
> Subject: [PATCHv2 1/8] drm/i915/histogram: Define registers for histogram
> 
> Add the register/bit definitions for global histogram.
> 
> v2: Intended the register contents, removed unused regs (Jani)

Adding Bpsec references for register definitions would help 
Other than that LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal at intel.com>

> 
> Signed-off-by: Arun R Murthy <arun.r.murthy at intel.com>
> ---
>  .../drm/i915/display/intel_histogram_regs.h   | 48 +++++++++++++++++++
>  1 file changed, 48 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_histogram_regs.h
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h
> b/drivers/gpu/drm/i915/display/intel_histogram_regs.h
> new file mode 100644
> index 000000000000..1252b4f339a6
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __INTEL_HISTOGRAM_REGS_H__
> +#define __INTEL_HISTOGRAM_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +/* GLOBAL_HIST related registers */
> +#define _DPST_CTL_A					0x490C0
> +#define _DPST_CTL_B					0x491C0
> +#define DPST_CTL(pipe)
> 	_MMIO_PIPE(pipe, _DPST_CTL_A, _DPST_CTL_B)
> +#define  DPST_CTL_IE_HIST_EN				REG_BIT(31)
> +#define  DPST_CTL_RESTORE				REG_BIT(28)
> +#define  DPST_CTL_IE_MODI_TABLE_EN			REG_BIT(27)
> +#define  DPST_CTL_HIST_MODE				REG_BIT(24)
> +#define  DPST_CTL_ENHANCEMENT_MODE_MASK
> 	REG_GENMASK(14, 13)
> +#define  DPST_CTL_EN_MULTIPLICATIVE
> 	REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2)
> +#define  DPST_CTL_IE_TABLE_VALUE_FORMAT			REG_BIT(15)
> +#define  DPST_CTL_BIN_REG_FUNC_SEL			REG_BIT(11)
> +#define  DPST_CTL_BIN_REG_FUNC_TC
> 	REG_FIELD_PREP(DPST_CTL_BIN_REG_FUNC_SEL, 0)
> +#define  DPST_CTL_BIN_REG_FUNC_IE
> 	REG_FIELD_PREP(DPST_CTL_BIN_REG_FUNC_SEL, 1)
> +#define  DPST_CTL_BIN_REG_MASK
> 	REG_GENMASK(6, 0)
> +#define  DPST_CTL_BIN_REG_CLEAR
> 	REG_FIELD_PREP(DPST_CTL_BIN_REG_MASK, 0)
> +#define  DPST_CTL_IE_TABLE_VALUE_FORMAT_2INT_8FRAC
> 	REG_FIELD_PREP(DPST_CTL_IE_TABLE_VALUE_FORMAT, 1)
> +#define  DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC
> 	REG_FIELD_PREP(DPST_CTL_IE_TABLE_VALUE_FORMAT, 0)
> +#define  DPST_CTL_HIST_MODE_YUV
> 	REG_FIELD_PREP(DPST_CTL_HIST_MODE, 0)
> +#define  DPST_CTL_HIST_MODE_HSV
> 	REG_FIELD_PREP(DPST_CTL_HIST_MODE, 1)
> +
> +#define _DPST_GUARD_A					0x490C8
> +#define _DPST_GUARD_B					0x491C8
> +#define DPST_GUARD(pipe)				_MMIO_PIPE(pipe,
> _DPST_GUARD_A, _DPST_GUARD_B)
> +#define  DPST_GUARD_HIST_INT_EN				REG_BIT(31)
> +#define  DPST_GUARD_HIST_EVENT_STATUS			REG_BIT(30)
> +#define  DPST_GUARD_INTERRUPT_DELAY_MASK
> 	REG_GENMASK(29, 22)
> +#define  DPST_GUARD_INTERRUPT_DELAY(val)
> 	REG_FIELD_PREP(DPST_GUARD_INTERRUPT_DELAY_MASK, val)
> +#define  DPST_GUARD_THRESHOLD_GB_MASK
> 	REG_GENMASK(21, 0)
> +#define  DPST_GUARD_THRESHOLD_GB(val)
> 	REG_FIELD_PREP(DPST_GUARD_THRESHOLD_GB_MASK, val)
> +
> +#define _DPST_BIN_A					0x490C4
> +#define _DPST_BIN_B					0x491C4
> +#define DPST_BIN(pipe)
> 	_MMIO_PIPE(pipe, _DPST_BIN_A, _DPST_BIN_B)
> +#define  DPST_BIN_DATA_MASK
> 	REG_GENMASK(23, 0)
> +#define  DPST_BIN_BUSY					REG_BIT(31)
> +
> +#endif /* __INTEL_HISTOGRAM_REGS_H__ */
> --
> 2.25.1