[PATCHv4 7/8] drm/i915/histogram: Histogram changes for Display 20+

[Murthy, Arun R]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal at intel.com>
> Sent: Wednesday, November 20, 2024 3:55 PM
> To: Murthy, Arun R <arun.r.murthy at intel.com>; intel-xe at lists.freedesktop.org;
> intel-gfx at lists.freedesktop.org; dri-devel at lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy at intel.com>
> Subject: RE: [PATCHv4 7/8] drm/i915/histogram: Histogram changes for Display
> 20+
> 
> 
> 
> > -----Original Message-----
> > From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of
> > Arun R Murthy
> > Sent: Tuesday, November 19, 2024 4:15 PM
> > To: intel-xe at lists.freedesktop.org; intel-gfx at lists.freedesktop.org;
> > dri- devel at lists.freedesktop.org
> > Cc: Murthy, Arun R <arun.r.murthy at intel.com>
> > Subject: [PATCHv4 7/8] drm/i915/histogram: Histogram changes for
> > Display
> > 20+
> >
> > In Display 20+, new registers are added for setting index, reading
> > histogram and writing the IET.
> 
> Bspec reference for new registers being added please
> 
> >
> > v2: Removed duplicate code (Jani)
> > v3: Moved histogram core changes to earlier patches (Jani/Suraj)
> > v4: Rebased after addressing comments on patch 1
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy at intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_histogram.c    | 111 +++++++++++++-----
> >  .../drm/i915/display/intel_histogram_regs.h   |  25 ++++
> >  2 files changed, 105 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c
> > b/drivers/gpu/drm/i915/display/intel_histogram.c
> > index fdcc64677e96..beaad9256e01 100644
> > --- a/drivers/gpu/drm/i915/display/intel_histogram.c
> > +++ b/drivers/gpu/drm/i915/display/intel_histogram.c
> > @@ -29,6 +29,51 @@ struct intel_histogram {
> >  	u32 bin_data[HISTOGRAM_BIN_COUNT];
> >  };
> >
> > +static void set_bin_index_0(struct intel_display *display, enum pipe
> > +pipe) {
> > +	if (DISPLAY_VER(display) >= 20)
> > +		intel_de_rmw(display, DPST_IE_INDEX(pipe),
> > +			     DPST_IE_BIN_INDEX_MASK,
> > DPST_IE_BIN_INDEX(0));
> > +	else
> > +		intel_de_rmw(display, DPST_CTL(pipe),
> > +			     DPST_CTL_BIN_REG_FUNC_SEL |
> > DPST_CTL_BIN_REG_MASK,
> > +			     DPST_CTL_BIN_REG_FUNC_IE |
> > DPST_CTL_BIN_REG_CLEAR); }
> > +
> > +static void write_iet(struct intel_display *display, enum pipe pipe,
> > +			      u32 *data)
> > +{
> > +	int i;
> > +
> > +	if (DISPLAY_VER(display) >= 20) {
> > +		for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) {
> > +			intel_de_rmw(display, DPST_IE_BIN(pipe),
> > +				     DPST_IE_BIN_DATA_MASK,
> > +				     DPST_IE_BIN_DATA(data[i]));
> > +			drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n",
> > +				       i, data[i]);
> > +		}
> > +	} else {
> > +		for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) {
> > +			intel_de_rmw(display, DPST_BIN(pipe),
> > +				     DPST_BIN_DATA_MASK, data[i]);
> > +			drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n",
> > +				       i, data[i]);
> > +		}
> > +	}
> > +}
> 
> The above code can be configured as shown below
> 
> int i;
> int register_base, data_mask;
> 
> if (DISPLAY_VER(display) >= 20) {
>     register_base = DPST_IE_BIN(pipe);
>     data_mask = DPST_IE_BIN_DATA_MASK;
> } else {
>     register_base = DPST_BIN(pipe);
>     data_mask = DPST_BIN_DATA_MASK;
> }
> 
> for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) {
>     intel_de_rmw(display, register_base, data_mask, data[i]);
>     drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]); }
> 

Writing the data[i] to be writing to the reg bit config also varies.
So rewriting this code within the for loop to optimize the code.

Thanks and Regards,
Arun R Murthy
-------------------