[PATCH 0/5] clk: Fix simple video pipelines on i.MX8

[Liu Ying]

Hi Miquel,

On 11/22/2024, Miquel Raynal wrote:
> Recent changes in the clock tree have set CLK_SET_RATE_PARENT to the two
> LCDIF pixel clocks. The idea is, instead of using assigned-clock
> properties to set upstream PLL rates to high frequencies and hoping that
> a single divisor (namely media_disp[12]_pix) will be close enough in
> most cases, we should tell the clock core to use the PLL to properly
> derive an accurate pixel clock rate in the first place. Here is the
> situation.
> 
> [Before ff06ea04e4cf ("clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate")]
> 
> Before setting CLK_SET_RATE_PARENT to the media_disp[12]_pix clocks, the sequence of events was:
> - PLL is assigned to a high rate,
> - media_disp[12]_pix is set to approximately freq A by using a single divisor,
> - media_ldb is set to approximately freq 7*A by using another single divisor.
> => The display was working, but the pixel clock was inaccurate.
> 
> [After ff06ea04e4cf ("clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate")]
> 
> After setting CLK_SET_RATE_PARENT to the media_disp[12]_pix clocks, the
> sequence of events became:
> - media_disp[12]_pix is set to freq A by using a divisor of 1 and
>   setting video_pll1 to freq A.
> - media_ldb is trying to compute its divisor to set freq 7*A, but the
>   upstream PLL is to low, it does not recompute it, so it ends up
>   setting a divisor of 1 and being at freq A instead of 7*A.
> => The display is sadly no longer working
> 
> [After applying PATCH "clk: imx: clk-imx8mp: Allow LDB serializer clock reconfigure parent rate"]
> 
> This is a commit from Marek, which is, I believe going in the right
> direction, so I am including it. Just with this change, the situation is
> slightly different, but the result is the same:
> - media_disp[12]_pix is set to freq A by using a divisor of 1 and
>   setting video_pll1 to freq A.
> - media_ldb is set to 7*A by using a divisor of 1 and setting video_pll1
>   to freq 7*A.
>   /!\ This as the side effect of changing media_disp[12]_pix from freq A
>   to freq 7*A.

Although I'm not of a fan of setting CLK_SET_RATE_PARENT flag to the
LDB clock and pixel clocks, would it work if the pixel clock rate is
set after the LDB clock rate is set in fsl_ldb_atomic_enable()?  The
pixel clock can be got from LDB's remote input LCDIF DT node by
calling of_clk_get_by_name() in fsl_ldb_probe() like the below patch
does. Similar to setting pixel clock rate, I think a chance is that
pixel clock enablement can be moved from LCDIF driver to
fsl_ldb_atomic_enable() to avoid on-the-fly division ratio change.

https://patchwork.kernel.org/project/linux-clk/patch/20241114065759.3341908-6-victor.liu@nxp.com/

Actually, one sibling patch of the above patch reverts ff06ea04e4cf
because I thought "fixed PLL rate" is the only solution, though I'm
discussing any alternative solution of "dynamically changeable PLL
rate" with Marek in the thread of the sibling patch.

BTW, as you know the LDB clock rate is 3.5x faster than the pixel
clock rate in dual-link LVDS use cases, the lowest PLL rate needs to
be explicitly set to 7x faster than the pixel clock rate *before*
LDB clock rate is set.  This way, the pixel clock would be derived
from the PLL with integer division ratio = 7, not the unsupported
3.5.

pixel    LDB         PLL
A        3.5*A       7*A      --> OK
A        3.5*A       3.5*A    --> not OK

> => The display is still not working
> 
> [After applying this series]
> 
> The goal of the following patches is to prevent clock subtree walks to
> "just recalculate" the pixel clocks, ignoring the fact that they should
> no longer change. They should adapt their divisors to the new upstream
> rates instead. As a result, the display pipeline is working again.
> 
> Note: if more than one display is connected, we need the LDB driver to
> act accordingly, thus the LDB driver must be adapted. Also, if accurate
> pixel clocks are not possible with two different displays, we will still
> need (at least for now) to make sure one of them is reparented to
> another PLL, like the audio PLL (but audio PLL are of a different kind,
> and are slightly less accurate).
> 
> So this series aims at fixing the i.MX8MP display pipeline for simple
> setups. Said otherwise, returning to the same level of support as
> before, but with (hopefully) more accurate frequencies. I believe this
> approach manages to fix both Marek situation and all people using a
> straightforward LCD based setup. For more complex setups, we need more
> smartness from DRM and clk, but this is gonna take a bit of time.
> 
> ---
> Marek Vasut (1):
>       clk: imx: clk-imx8mp: Allow LDB serializer clock reconfigure parent rate
> 
> Miquel Raynal (4):
>       clk: Add a helper to determine a clock rate
>       clk: Split clk_calc_subtree()
>       clk: Add flag to prevent frequency changes when walking subtrees
>       clk: imx: imx8mp: Prevent media clocks to be incompatibly changed
> 
>  drivers/clk/clk.c            | 39 ++++++++++++++++++++++++++++++++-------
>  drivers/clk/imx/clk-imx8mp.c |  6 +++---
>  include/linux/clk-provider.h |  2 ++
>  3 files changed, 37 insertions(+), 10 deletions(-)
> ---
> base-commit: 62facaf164585923d081eedcb6871f4ff3c2e953
> change-id: 20241121-ge-ian-debug-imx8-clk-tree-bd325aa866f1
> 
> Best regards,

-- 
Regards,
Liu Ying