[PATCH v2] drm/rockchip: vop2: fix rk3588 dp+dsi maxclk verification

Sebastian Reichel sebastian.reichel at collabora.com
Fri Nov 22 18:50:47 UTC 2024


Hi,

On Fri, Nov 15, 2024 at 04:11:31PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner at cherry.de>
> 
> The clock is in Hz while the value checked against is in kHz, so
> actual frequencies will never be able to be below to max value.
> Fix this by specifying the max-value in Hz too.
> 
> Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
> Signed-off-by: Heiko Stuebner <heiko.stuebner at cherry.de>
> Reviewed-by: Quentin Schulz <quentin.schulz at cherry.de>
> Acked-by: Andy Yan<andyshrk at 163.com>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel at collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel at collabora.com>

-- Sebastian

> changes in v2:
> - drop the separate vp3-config patch, as vp3 will always get the leftover
>   resources, so _should_ be fine (Andy)
> - fix error output to also report Hz for the value in Hz (Quentin)
> - add received Reviews+Acks
> 
>  drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> index 9ad025aa9ab0..0c8ec7220fbe 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> @@ -1864,9 +1864,9 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
>  		else
>  			dclk_out_rate = v_pixclk >> 2;
>  
> -		dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
> +		dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
>  		if (!dclk_rate) {
> -			drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld KHZ\n",
> +			drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld Hz\n",
>  				dclk_out_rate);
>  			return 0;
>  		}
> @@ -1881,9 +1881,9 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
>  		 * dclk_rate = N * dclk_core_rate N = (1,2,4 ),
>  		 * we get a little factor here
>  		 */
> -		dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
> +		dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
>  		if (!dclk_rate) {
> -			drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld KHZ\n",
> +			drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld Hz\n",
>  				dclk_out_rate);
>  			return 0;
>  		}
> -- 
> 2.45.2
> 
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