[EXT] Re: [PATCH v18 6/8] phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ
Dmitry Baryshkov
dmitry.baryshkov at linaro.org
Sat Nov 30 08:29:43 UTC 2024
On Tue, Nov 26, 2024 at 02:12:19PM +0000, Sandor Yu wrote:
>
> >
> > On Tue, Nov 05, 2024 at 02:05:51PM +0000, Sandor Yu wrote:
> > > >
> > > > On Tue, Oct 29, 2024 at 02:02:14PM +0800, Sandor Yu wrote:
> > > > > Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.
> > > > >
> > > > > Cadence HDP-TX PHY could be put in either DP mode or HDMI mode
> > > > > base on the configuration chosen.
> > > > > DisplayPort or HDMI PHY mode is configured in the driver.
> > > > >
> > > > > Signed-off-by: Sandor Yu <Sandor.yu at nxp.com>
> > > > > Signed-off-by: Alexander Stein <alexander.stein at ew.tq-group.com>
> > > > > ---
> > > > > v17->v18:
> > > > > - fix build error as code rebase to latest kernel version.
> > > > >
> > > > > drivers/phy/freescale/Kconfig | 10 +
> > > > > drivers/phy/freescale/Makefile | 1 +
> > > > > drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1337
> > > > ++++++++++++++++++
> > > > > 3 files changed, 1348 insertions(+) create mode 100644
> > > > > drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c
> > > > >
> > > > > diff --git a/drivers/phy/freescale/Kconfig
> > > > > b/drivers/phy/freescale/Kconfig index dcd9acff6d01a..2b1210367b31c
> > > > > 100644
> > > > > --- a/drivers/phy/freescale/Kconfig
> > > > > +++ b/drivers/phy/freescale/Kconfig
> >
> > [...]
> >
> > I'm sorry, my email client cut the email.
> >
> > > > > +static int cdns_hdptx_dp_configure(struct phy *phy,
> > > > > + union phy_configure_opts
> > *opts) {
> > > > > + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> > > > > +
> > > > > + cdns_phy->dp.link_rate = opts->dp.link_rate;
> > > > > + cdns_phy->dp.lanes = opts->dp.lanes;
> > > >
> > > > Shouldn't this be conditional on set_rate / set_lanes ?
> > >
> > > PHY do not support reconfigure link rate and lane count.
> >
> > So, you don't support reconfiguring the rate / count, but you still copy the new
> > rate and lanes into your driver data. That sounds strange.
>
> The PHY will use link rate and lane count to configure its registers
I'm not sure if I follow it. Do you mean that rate / count configuration
is static?
--
With best wishes
Dmitry
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