[PATCH v5 1/1] drm/mediatek: Fix get efuse issue for MT8188 DPTX

[Fei Shao]

On Mon, Sep 23, 2024 at 9:26 PM Liankun Yang <liankun.yang at mediatek.com> wrote:
>
> Update efuse data for MT8188 displayport.
>
> The DP monitor can not display when DUT connected to USB-c to DP dongle.
> Analysis view is invalid DP efuse data.
>
> Fixes: 350c3fe907fb ("drm/mediatek: dp: Add support MT8188 dp/edp function")
> Reviewed-by: Matthias Brugger <matthias.bgg at gmail.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Signed-off-by: Liankun Yang <liankun.yang at mediatek.com>

Tested on MT8188-based Lenovo Chromebook Duet 11.

Reviewed-by: Fei Shao <fshao at chromium.org>
Tested-by: Fei Shao <fshao at chromium.org>


> ---
> Changes in V5:
> - No change.
> Per suggestion from the previous thread:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20240905124041.3658-1-liankun.yang@mediatek.com/
>
> Changes in V4:
> - Remove excess newlines.
> Per suggestion from the previous thread:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20240903121028.20689-1-liankun.yang@mediatek.com/
>
> Changes in V3
> - Update change log position in commit message.
> Per suggestion from the previous thread:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20240902133736.16461-1-liankun.yang@mediatek.com/
>
> Changes in V2
> - Add Fixes tag.
> - Update the commit title.
> - Update the commit description.
> Per suggestion from the previous thread:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20240510061716.31103-1-liankun.yang@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_dp.c | 85 ++++++++++++++++++++++++++++++-
>  1 file changed, 84 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index d8796a904eca..f2bee617f063 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -145,6 +145,89 @@ struct mtk_dp_data {
>         u16 audio_m_div2_bit;
>  };
>
> +static const struct mtk_dp_efuse_fmt mt8188_dp_efuse_fmt[MTK_DP_CAL_MAX] = {
> +       [MTK_DP_CAL_GLB_BIAS_TRIM] = {
> +               .idx = 0,
> +               .shift = 10,
> +               .mask = 0x1f,
> +               .min_val = 1,
> +               .max_val = 0x1e,
> +               .default_val = 0xf,
> +       },
> +       [MTK_DP_CAL_CLKTX_IMPSE] = {
> +               .idx = 0,
> +               .shift = 15,
> +               .mask = 0xf,
> +               .min_val = 1,
> +               .max_val = 0xe,
> +               .default_val = 0x8,
> +       },
> +       [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] = {
> +               .idx = 1,
> +               .shift = 0,
> +               .mask = 0xf,
> +               .min_val = 1,
> +               .max_val = 0xe,
> +               .default_val = 0x8,
> +       },
> +       [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] = {
> +               .idx = 1,
> +               .shift = 8,
> +               .mask = 0xf,
> +               .min_val = 1,
> +               .max_val = 0xe,
> +               .default_val = 0x8,
> +       },
> +       [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] = {
> +               .idx = 1,
> +               .shift = 16,
> +               .mask = 0xf,
> +               .min_val = 1,
> +               .max_val = 0xe,
> +               .default_val = 0x8,
> +       },
> +       [MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] = {
> +               .idx = 1,
> +               .shift = 24,
> +               .mask = 0xf,
> +               .min_val = 1,
> +               .max_val = 0xe,
> +               .default_val = 0x8,
> +       },
> +       [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] = {
> +               .idx = 1,
> +               .shift = 4,
> +               .mask = 0xf,
> +               .min_val = 1,
> +               .max_val = 0xe,
> +               .default_val = 0x8,
> +       },
> +       [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] = {
> +               .idx = 1,
> +               .shift = 12,
> +               .mask = 0xf,
> +               .min_val = 1,
> +               .max_val = 0xe,
> +               .default_val = 0x8,
> +       },
> +       [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] = {
> +               .idx = 1,
> +               .shift = 20,
> +               .mask = 0xf,
> +               .min_val = 1,
> +               .max_val = 0xe,
> +               .default_val = 0x8,
> +       },
> +       [MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] = {
> +               .idx = 1,
> +               .shift = 28,
> +               .mask = 0xf,
> +               .min_val = 1,
> +               .max_val = 0xe,
> +               .default_val = 0x8,
> +       },
> +};
> +
>  static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {
>         [MTK_DP_CAL_GLB_BIAS_TRIM] = {
>                 .idx = 3,
> @@ -2771,7 +2854,7 @@ static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, mtk_dp_resume);
>  static const struct mtk_dp_data mt8188_dp_data = {
>         .bridge_type = DRM_MODE_CONNECTOR_DisplayPort,
>         .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
> -       .efuse_fmt = mt8195_dp_efuse_fmt,
> +       .efuse_fmt = mt8188_dp_efuse_fmt,
>         .audio_supported = true,
>         .audio_pkt_in_hblank_area = true,
>         .audio_m_div2_bit = MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
> --
> 2.45.2
>
>