[PATCH] drm/bridge: tc358767: Improve DPI output pixel clock accuracy

[Maxime Ripard]

On Sat, Oct 26, 2024 at 06:11:12AM +0200, Marek Vasut wrote:
> The Pixel PLL is not very capable and may come up with wildly inaccurate
> clock. Since DPI panels are often tolerant to slightly higher pixel clock
> without being operated outside of specification, calculate two Pixel PLL
> settings for DPI output, one for desired output pixel clock and one for
> output pixel clock with 1% increase, and then pick the result which is
> closer to the desired pixel clock and use it as the Pixel PLL settings.

The typical tolerance we've used is .5%, which is recommended by VESA in
several specs. Differing from it for a good reason is ok I guess, but
you need to document why.

Maxime
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 273 bytes
Desc: not available
URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20241028/6c649b93/attachment.sig>