[PATCH v4 03/13] drm/bridge: fsl-ldb: Use clk_round_rate() to validate "ldb" clock rate

[Liu Ying]

Hi Maxime,

On 10/30/2024, Maxime Ripard wrote:
> On Mon, Oct 28, 2024 at 10:37:30AM +0800, Liu Ying wrote:
>> Multiple display modes could be read from a display device's EDID.
>> Use clk_round_rate() to validate the "ldb" clock rate for each mode
>> in drm_bridge_funcs::mode_valid() to filter unsupported modes out.
>>
>> Also, since this driver doesn't directly reference pixel clock, use
>> clk_round_rate() to validate the pixel clock rate against the "ldb"
>> clock if the "ldb" clock and the pixel clock are sibling in clock
>> tree.  This is not done in display controller driver because
>> drm_crtc_helper_funcs::mode_valid() may not decide to do the
>> validation or not if multiple encoders are connected to the CRTC,
>> e.g., i.MX93 LCDIF may connect with MIPI DSI controller, LDB and
>> parallel display output simultaneously.
>>
>> Signed-off-by: Liu Ying <victor.liu at nxp.com>
>> ---
>> Note that this patch depends on a patch in shawnguo/imx/fixes:
>> https://patchwork.kernel.org/project/linux-arm-kernel/patch/20241017031146.157996-1-marex@denx.de/
> 
> I still believe that the root cause of this issue is your clock tree and
> driver setup, and since I've asked for explanations and didn't get any,
> I don't really see how we can move forward here.

Since you asked for a description at *somewhere* in another thread[1],
can you please suggest a place where this could happen?

[1] https://lore.kernel.org/imx/47d92ae0-c71a-4c18-9ad7-432c0f70a31f@nxp.com/T/#m587e6a25bdab542d5d99abbf01caaca89495b1d5

> 
> Maxime

-- 
Regards,
Liu Ying