[PATCH v2] drm/i915/guc: Enable PXP GuC autoteardown flow

[Teres Alexis, Alan Previn]

LGTM:

Reviewed-by: Alan Previn <alan.previn.teres.alexis at intel.com>

On Fri, 2024-09-06 at 10:40 -0700, John.C.Harrison at Intel.com wrote:
> From: Juston Li <juston.li at intel.com>
> 
> This feature flag enables GuC autoteardown which allows for a grace
> period before session teardown.
> 
> Also add a HAS_PXP() helper to share with the other place that wants
> to check.
> 
> Signed-off-by: Juston Li <juston.li at intel.com>
> Signed-off-by: John Harrison <John.C.Harrison at Intel.com>
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c      | 8 ++++++++
>  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
>  drivers/gpu/drm/i915/i915_drv.h             | 3 +++
>  drivers/gpu/drm/i915/pxp/intel_pxp.c        | 2 +-
>  4 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 097fc6bd1285e..5949ff0b0161f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -239,8 +239,16 @@ static u32 guc_ctl_debug_flags(struct intel_guc *guc)
>  
>  static u32 guc_ctl_feature_flags(struct intel_guc *guc)
>  {
> +       struct intel_gt *gt = guc_to_gt(guc);
>         u32 flags = 0;
>  
> +       /*
> +        * Enable PXP GuC autoteardown flow.
> +        * NB: MTL does things differently.
> +        */
> +       if (HAS_PXP(gt->i915) && !IS_METEORLAKE(gt->i915))
> +               flags |= GUC_CTL_ENABLE_GUC_PXP_CTL;
> +
>         if (!intel_guc_submission_is_used(guc))
>                 flags |= GUC_CTL_DISABLE_SCHEDULER;
>  
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 263c9c3f6a034..4ce6e2332a63f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -105,6 +105,7 @@
>  #define   GUC_WA_ENABLE_TSC_CHECK_ON_RC6       BIT(22)
>  
>  #define GUC_CTL_FEATURE                        2
> +#define   GUC_CTL_ENABLE_GUC_PXP_CTL   BIT(1)
>  #define   GUC_CTL_ENABLE_SLPC          BIT(2)
>  #define   GUC_CTL_DISABLE_SCHEDULER    BIT(14)
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 39f6614a0a99a..faeba9732422f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -693,6 +693,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  #define HAS_RPS(i915)  (INTEL_INFO(i915)->has_rps)
>  
> +#define HAS_PXP(i915) \
> +       (IS_ENABLED(CONFIG_DRM_I915_PXP) && INTEL_INFO(i915)->has_pxp)
> +
>  #define HAS_HECI_PXP(i915) \
>         (INTEL_INFO(i915)->has_heci_pxp)
>  
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 75278e78ca90e..5e0bf776aac0f 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -170,7 +170,7 @@ static struct intel_gt *find_gt_for_required_teelink(struct drm_i915_private *i9
>  
>  static struct intel_gt *find_gt_for_required_protected_content(struct drm_i915_private *i915)
>  {
> -       if (!IS_ENABLED(CONFIG_DRM_I915_PXP) || !INTEL_INFO(i915)->has_pxp)
> +       if (!HAS_PXP(i915))
>                 return NULL;
>  
>         /*