[PATCH v2 3/3] drm/nouveau: Add drm_panic support for nv50+

[Ilia Mirkin]

On Wed, Sep 11, 2024 at 10:19 AM Jocelyn Falempe <jfalempe at redhat.com>
wrote:

> On 06/09/2024 21:36, James Jones wrote:
> > Right, there are 3 iterations of block linear tiling actually. NV50 does
> > support scanout of block linear surfaces. All block-linear-capable GPUs
> > do. The 3 generations are:
> >
> > NV5x/G8x/GTXXX line: Original block size.
> > GFXXX(nvc0 I believe in nouveau terms)-GV100: double the block height I
> > believe.
> > GTXXX+: Same block size, but the layout within a block is subtly
> > different, at least as visible in CPU mappings.
> >
>
> I'm looking at how to check for specific chip in nouveau, and fix the
> tiling for other cards than Turing.
> It looks like in most case nouveau uses device->info.chipset, with
> hardcoded hex value. so for nvc0+ I should check device->info.chipset >=
> 0xc0 ?
>
> chipset < c0 : block_height 4, "old layout"
> chipset >= c0 : block_height 8, "old layout"
> chispet >= ?? : block_height 8, "new layout"
>
> For testing, I have at hand a GTX1650 (Turing) and an old Geforce
> 8800GTS (Tesla?), so it's a NV92, and still uses this nv50+ code ?
>

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c#n2399

So probably >= 0x160

There should also be a device->card_type which is an enum that you can use
too, depending on what you have available? Set here:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c#n3177

Once you have a patch tested, ideally someone with the hardware should test
on a >= fermi && < turing card.

Hope this helps,

  -ilia
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