[PATCH v1] drm/amd/display: fix typo in the comment

[Alex Deucher]

Applied.  Thanks!

Alex

On Thu, Sep 12, 2024 at 3:56 AM Yan Zhen <yanzhen at vivo.com> wrote:
>
> Correctly spelled comments make it easier for the reader to understand
> the code.
>
> Replace 'maxium' with 'maximum' in the comment &
> replace 'diffculty' with 'difficulty' in the comment &
> replace 'suppluy' with 'supply' in the comment &
> replace 'Congiuration' with 'Configuration' in the comment &
> replace 'eanbled' with 'enabled' in the comment.
>
> Signed-off-by: Yan Zhen <yanzhen at vivo.com>
> ---
>  drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c       | 2 +-
>  drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 6 +++---
>  drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 2 +-
>  3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
> index e47e9db062f4..d70a3549e05a 100644
> --- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
> @@ -569,7 +569,7 @@ static void calculate_bandwidth(
>                                 break;
>                         }
>                         data->lb_partitions[i] = bw_floor2(bw_div(data->lb_size_per_component[i], data->lb_line_pitch), bw_int_to_fixed(1));
> -                       /*clamp the partitions to the maxium number supported by the lb*/
> +                       /* clamp the partitions to the maximum number supported by the lb */
>                         if ((surface_type[i] != bw_def_graphics || dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1)) {
>                                 data->lb_partitions_max[i] = bw_int_to_fixed(10);
>                         }
> diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
> index 547dfcc80fde..d851c081e376 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
> @@ -8926,7 +8926,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc
>
>         // The prefetch scheduling should only be calculated once as per AllowForPStateChangeOrStutterInVBlank requirement
>         // If the AllowForPStateChangeOrStutterInVBlank requirement is not strict (i.e. only try those power saving feature
> -       // if possible, then will try to program for the best power saving features in order of diffculty (dram, fclk, stutter)
> +       // if possible, then will try to program for the best power saving features in order of difficulty (dram, fclk, stutter)
>         s->iteration = 0;
>         s->MaxTotalRDBandwidth = 0;
>         s->AllPrefetchModeTested = false;
> @@ -9977,7 +9977,7 @@ void dml_core_get_row_heights(
>         dml_print("DML_DLG: %s: GPUVMMinPageSizeKBytes = %u\n", __func__, GPUVMMinPageSizeKBytes);
>  #endif
>
> -       // just suppluy with enough parameters to calculate meta and dte
> +       // just supply with enough parameters to calculate meta and dte
>         CalculateVMAndRowBytes(
>                         0, // dml_bool_t ViewportStationary,
>                         1, // dml_bool_t DCCEnable,
> @@ -10110,7 +10110,7 @@ dml_bool_t dml_mode_support(
>  /// Note: In this function, it is assumed that DCFCLK, SOCCLK freq are the state values, and mode_program will just use the DML calculated DPPCLK and DISPCLK
>  /// @param mode_lib mode_lib data struct that house all the input/output/bbox and calculation values.
>  /// @param state_idx Power state idx chosen
> -/// @param display_cfg Display Congiuration
> +/// @param display_cfg Display Configuration
>  /// @param call_standalone Calling mode_programming without calling mode support.  Some of the "support" struct member will be pre-calculated before doing mode programming
>  /// TODO: Add clk_cfg input, could be useful for standalone mode
>  dml_bool_t dml_mode_programming(
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
> index 42c52284a868..355823530aa4 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
> @@ -455,7 +455,7 @@ bool dcn30_mmhubbub_warmup(
>         struct mcif_wb *mcif_wb;
>         struct mcif_warmup_params warmup_params = {0};
>         unsigned int  i, i_buf;
> -       /*make sure there is no active DWB eanbled */
> +       /* make sure there is no active DWB enabled */
>         for (i = 0; i < num_dwb; i++) {
>                 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
>                 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
> --
> 2.34.1
>