[PATCH v3 1/4] dt-bindings: display: bridge: add sam9x75-mipi-dsi binding

[Manikandan.M at microchip.com]

On 17/09/24 6:08 pm, Conor Dooley wrote:
> On Tue, Sep 17, 2024 at 03:16:53AM +0000,Manikandan.M at microchip.com  wrote:
>> Hi Conor,
>>
>> On 14/08/24 7:29 pm, Conor Dooley wrote:
>>> On Wed, Aug 14, 2024 at 04:22:53PM +0530, Manikandan Muralidharan wrote:
>>>> Add the 'sam9x75-mipi-dsi' compatible binding, which describes the
>>>> Microchip's specific wrapper for the Synopsys DesignWare MIPI DSI HOST
>>>> Controller for the sam9x75 series System-on-Chip (SoC) devices.
>>>>
>>>> Signed-off-by: Manikandan Muralidharan<manikandan.m at microchip.com>
>>>> ---
>>>> changes in v3:
>>>> - Describe the clocks used
>>>>
>>>> changes in v2:
>>>> - List the clocks with description
>>>> - remove describing 'remove-endpoint' properties
>>>> - remove unused label, node and fix example DT indentation
>>>> - cosmetic fixes
>>>> ---
>>>>    .../bridge/microchip,sam9x75-mipi-dsi.yaml    | 116 ++++++++++++++++++
>>>>    1 file changed, 116 insertions(+)
>>>>    create mode 100644 Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml
>>>> new file mode 100644
>>>> index 000000000000..3c86f0cd49e9
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml
>>>> @@ -0,0 +1,116 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id:http://devicetree.org/schemas/display/bridge/microchip,sam9x75-mipi-dsi.yaml#
>>>> +$schema:http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Microchip SAM9X75 MIPI DSI Controller
>>>> +
>>>> +maintainers:
>>>> +  - Manikandan Muralidharan<manikandan.m at microchip.com>
>>>> +
>>>> +description:
>>>> +  Microchip specific extensions or wrapper to the Synopsys Designware MIPI DSI.
>>>> +  The MIPI Display Serial Interface (DSI) Host Controller implements all
>>>> +  protocol functions defined in the MIPI DSI Specification.The DSI Host
>>>> +  provides an interface between the LCD Controller (LCDC) and the MIPI D-PHY,
>>>> +  allowing communication with a DSI-compliant display.
>>>> +
>>>> +allOf:
>>>> +  - $ref: /schemas/display/dsi-controller.yaml#
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    const: microchip,sam9x75-mipi-dsi
>>>> +
>>>> +  reg:
>>>> +    maxItems: 1
>>>> +
>>>> +  clocks:
>>>> +    items:
>>>> +      - description:
>>>> +          Peripheral Bus Clock between LCDC and MIPI DPHY
>>>> +      - description:
>>>> +          MIPI DPHY Interface reference clock for PLL block
>>>> +
>>>> +  clock-names:
>>>> +    items:
>>>> +      - const: pclk
>>>> +      - const: refclk
>>>> +
>>>> +  microchip,sfr:
>>>> +    $ref: /schemas/types.yaml#/definitions/phandle
>>>> +    description:
>>>> +      phandle to Special Function Register (SFR) node.To enable the DSI/CSI
>>>> +      selection bit in SFR's ISS Configuration Register.
>>> I'm curious - why is this phandle required? How many SFR nodes are there
>>> on the platform?
>> This phandle is to map the memory region of SFR node and configure the
>> DSI bit in the SFR's ISS configuration register.
>> currently there is only one SFR node in this platform.
> What does "currently" mean? The platform either has one or it does not,
> currently makes it sound like it has more than one but the dts only has
> one.
Apologies, I would like to clarify the statement that this platform only 
has one 32-bit special function register implemented.
-- 
Thanks and Regards,
Manikandan M.