[PATCH v2 4/5] drm/i915/display: Add registers and compute the strength

[Jani Nikula]

On Tue, 17 Sep 2024, Nemesa Garg <nemesa.garg at intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84b05b57ad52..41c6c56d83d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2396,6 +2396,23 @@
>  			_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
>  			_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
>  
> +#define _SHARPNESS_CTL_A               0x682B0
> +#define SHARPNESS_CTL(trans)           _MMIO_PIPE2(dev_priv, trans, _SHARPNESS_CTL_A)

Oh, also, absolutely do not rely on implicit dev_priv variable in
there. Replace with display passed in explicitly. We've fixed this,
there are no implicit dev_priv variables used anywhere anymore. Do not
add new ones.

> +#define  FILTER_EN                      REG_BIT(31)
> +#define  FILTER_STRENGTH_MASK           REG_GENMASK(15, 8)
> +#define  FILTER_STRENGTH(x)             REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
> +#define  FILTER_SIZE_MASK               REG_GENMASK(1, 0)
> +#define  FILTER_SIZE(x)                 REG_FIELD_PREP(FILTER_SIZE_MASK, (x))
> +
> +#define _SHRPLUT_DATA_A                        0x682B8
> +#define SHRPLUT_DATA(trans)            _MMIO_PIPE2(dev_priv, trans, _SHRPLUT_DATA_A)
> +
> +#define _SHRPLUT_INDEX_A               0x682B4
> +#define SHRPLUT_INDEX(trans)           _MMIO_PIPE2(dev_priv, trans, _SHRPLUT_INDEX_A)
> +#define  INDEX_AUTO_INCR               REG_BIT(10)
> +#define  INDEX_VALUE_MASK              REG_GENMASK(4, 0)
> +#define  INDEX_VALUE(x)                        REG_FIELD_PREP(INDEX_VALUE_MASK, (x))
          ^ 3 spaces      ^ tabs

Also, do check the big comment near the top of i915_reg.h about style
for the macros.

BR,
Jani.

> +
>  /* Display Internal Timeout Register */
>  #define RM_TIMEOUT		_MMIO(0x42060)
>  #define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)

-- 
Jani Nikula, Intel