[PATCH v4] drm/mediatek: ovl: Add fmt_convert function pointer to driver data
CK Hu (胡俊光)
ck.hu at mediatek.com
Wed Sep 25 07:45:57 UTC 2024
Hi, Jason:
On Tue, 2024-09-24 at 09:49 +0800, Jason-JH.Lin wrote:
> OVL_CON_CLRFMT_MAN is a configuration for extending color format
> settings of DISP_REG_OVL_CON(n).
> It will change some of the original color format settings.
>
> Take the settings of (3 << 12) for example.
> - If OVL_CON_CLRFMT_MAN = 0 means OVL_CON_CLRFMT_RGBA8888.
> - If OVL_CON_CLRFMT_MAN = 1 means OVL_CON_CLRFMT_PARGB8888.
>
> Since OVL_CON_CLRFMT_MAN is not supported on previous SoCs,
> It breaks the OVL color format setting of MT8173.
>
> Therefore, the fmt_convert function pointer is added to the driver data
> and mtk_ovl_fmt_convert_with_blend is implemented for MT8192 and MT8195
> that support OVL_CON_CLRFMT_MAN, and mtk_ovl_fmt_convert is implemented
> for other SoCs that do not support it to solve the degradation problem.
This patch looks good to me, so
Reviewed-by: CK Hu <ck.hu at mediatek.com>
By this patch, only some SoC support pre-multiplied pixel format.
In [1], it declare that all SoC support pre-multiplied pixel format, so I think need another patch to let only some SoC support pre-multiplied.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/drivers/gpu/drm/mediatek?h=next-20240925&id=4225d5d5e779b859a6661130a3444eb4c5db77e5
>
> Fixes: a3f7f7ef4bfe ("drm/mediatek: Support "Pre-multiplied" blending in OVL")
> Signed-off-by: Jason-JH.Lin <jason-jh.lin at mediatek.com>
> Tested-by: Alper Nebi Yasak <alpernebiyasak at gmail.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 68 ++++++++++++++++++++++---
> 1 file changed, 61 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 89b439dcf3a6..8f7b7e07aeb1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -143,6 +143,7 @@ struct mtk_disp_ovl_data {
> unsigned int addr;
> unsigned int gmc_bits;
> unsigned int layer_nr;
> + unsigned int (*fmt_convert)(struct device *dev, struct mtk_plane_state *state);
> bool fmt_rgb565_is_0;
> bool smi_id_en;
> bool supports_afbc;
> @@ -386,13 +387,59 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
> DISP_REG_OVL_RDMA_CTRL(idx));
> }
>
> -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt,
> - unsigned int blend_mode)
> +static unsigned int mtk_ovl_fmt_convert(struct device *dev, struct mtk_plane_state *state)
> {
> - /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
> - * is defined in mediatek HW data sheet.
> - * The alphabet order in XXX is no relation to data
> - * arrangement in memory.
> + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
> + unsigned int fmt = state->pending.format;
> +
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return OVL_CON_CLRFMT_RGB565(ovl);
> + case DRM_FORMAT_BGR565:
> + return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
> + case DRM_FORMAT_RGB888:
> + return OVL_CON_CLRFMT_RGB888(ovl);
> + case DRM_FORMAT_BGR888:
> + return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_RGBX1010102:
> + case DRM_FORMAT_RGBA1010102:
> + return OVL_CON_CLRFMT_RGBA8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_BGRX1010102:
> + case DRM_FORMAT_BGRA1010102:
> + return OVL_CON_CLRFMT_BGRA8888;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XRGB2101010:
> + case DRM_FORMAT_ARGB2101010:
> + return OVL_CON_CLRFMT_ARGB8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_ABGR2101010:
> + return OVL_CON_CLRFMT_ABGR8888;
> + case DRM_FORMAT_UYVY:
> + return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
> + case DRM_FORMAT_YUYV:
> + return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
> + }
> +}
> +
> +static unsigned int mtk_ovl_fmt_convert_with_blend(struct device *dev,
> + struct mtk_plane_state *state)
> +{
> + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
> + unsigned int fmt = state->pending.format;
> + unsigned int blend_mode = state->base.pixel_blend_mode;
> +
> + /*
> + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the
> + * hardware data sheet and supports premultiplied color formats
> + * such as OVL_CON_CLRFMT_PARGB8888.
> */
> switch (fmt) {
> default:
> @@ -471,7 +518,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
> return;
> }
>
> - con = ovl_fmt_convert(ovl, fmt, blend_mode);
> + con = ovl->data->fmt_convert(dev, state);
> if (state->base.fb) {
> con |= OVL_CON_AEN;
> con |= state->base.alpha & OVL_CON_ALPHA;
> @@ -625,6 +672,7 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT2701,
> .gmc_bits = 8,
> .layer_nr = 4,
> + .fmt_convert = mtk_ovl_fmt_convert,
> .fmt_rgb565_is_0 = false,
> .formats = mt8173_formats,
> .num_formats = ARRAY_SIZE(mt8173_formats),
> @@ -634,6 +682,7 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT8173,
> .gmc_bits = 8,
> .layer_nr = 4,
> + .fmt_convert = mtk_ovl_fmt_convert,
> .fmt_rgb565_is_0 = true,
> .formats = mt8173_formats,
> .num_formats = ARRAY_SIZE(mt8173_formats),
> @@ -643,6 +692,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT8173,
> .gmc_bits = 10,
> .layer_nr = 4,
> + .fmt_convert = mtk_ovl_fmt_convert,
> .fmt_rgb565_is_0 = true,
> .formats = mt8173_formats,
> .num_formats = ARRAY_SIZE(mt8173_formats),
> @@ -652,6 +702,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT8173,
> .gmc_bits = 10,
> .layer_nr = 2,
> + .fmt_convert = mtk_ovl_fmt_convert,
> .fmt_rgb565_is_0 = true,
> .formats = mt8173_formats,
> .num_formats = ARRAY_SIZE(mt8173_formats),
> @@ -661,6 +712,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT8173,
> .gmc_bits = 10,
> .layer_nr = 4,
> + .fmt_convert = mtk_ovl_fmt_convert_with_blend,
> .fmt_rgb565_is_0 = true,
> .smi_id_en = true,
> .formats = mt8173_formats,
> @@ -671,6 +723,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT8173,
> .gmc_bits = 10,
> .layer_nr = 2,
> + .fmt_convert = mtk_ovl_fmt_convert_with_blend,
> .fmt_rgb565_is_0 = true,
> .smi_id_en = true,
> .formats = mt8173_formats,
> @@ -681,6 +734,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT8173,
> .gmc_bits = 10,
> .layer_nr = 4,
> + .fmt_convert = mtk_ovl_fmt_convert_with_blend,
> .fmt_rgb565_is_0 = true,
> .smi_id_en = true,
> .supports_afbc = true,
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