[PATCH 03/12] drm/i915/display: Add sharpness strength and winsize
Nautiyal, Ankit K
ankit.k.nautiyal at intel.com
Tue Apr 1 05:28:07 UTC 2025
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
> register
I think this is part of the subject, need to fix this.
>
> The strength value for sharpness is based on user input and
> the winsize is based on resolution. Set the casf_enable flag
> if there is a platform support and uapi strength is not zero.
> Once the sharpness is enabled then just update the strength
> bit of the register everytime whenever user changes the strength
> as enable bit and winsize bit remains constant.
>
> v2: Introduce get_config for casf[Ankit]
>
> Signed-off-by: Nemesa Garg <nemesa.garg at intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_casf.c | 99 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_casf.h | 17 ++++
> .../gpu/drm/i915/display/intel_casf_regs.h | 22 +++++
> .../drm/i915/display/intel_crtc_state_dump.c | 7 ++
> .../drm/i915/display/intel_display_types.h | 7 ++
> drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> drivers/gpu/drm/xe/Makefile | 1 +
> 8 files changed, 155 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h
> create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index c8fc271b33b7..a955960d09ec 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -230,6 +230,7 @@ i915-y += \
> display/intel_bios.o \
> display/intel_bo.o \
> display/intel_bw.o \
> + display/intel_casf.o \
> display/intel_cdclk.o \
> display/intel_cmtg.o \
> display/intel_color.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
> new file mode 100644
> index 000000000000..28f76b06fd8f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + *
> + */
> +#include "i915_reg.h"
> +#include "intel_casf.h"
> +#include "intel_casf_regs.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +
> +#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
> +#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
> +
> +/**
> + * DOC: Content Adaptive Sharpness Filter (CASF)
> + *
> + * From LNL onwards the display engine based adaptive
> + * sharpening filter is supported. This helps in
> + * improving the image quality. The display hardware
> + * uses one of the pipe scaler for implementing casf.
Use CASF.
Perhaps a line can be left here before beginning a new paragraph.
> + * It works on a region of pixels depending on the
CASF works...
Apart from the nitpicks above the patch looks good to me.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> + * tap size. The coefficients are used to generate an
> + * alpha value which is used to blend the sharpened image
> + * to original image.
> + */
> +
> +void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), 0,
> + FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
> +}
> +
> +static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
> +{
> + const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
> + u16 total_pixels = mode->hdisplay * mode->vdisplay;
> +
> + if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
> + crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
> + else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
> + crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
> + else
> + crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
> +}
> +
> +int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + if (!HAS_CASF(display))
> + return 0;
> +
> + if (crtc_state->uapi.sharpness_strength == 0) {
> + crtc_state->hw.casf_params.casf_enable = false;
> + crtc_state->hw.casf_params.strength = 0;
> + return 0;
> + }
> +
> + crtc_state->hw.casf_params.casf_enable = true;
> +
> + /*
> + * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
> + * Strength is from 0.0-14.9375 ie from 0-239.
> + * User can give value from 0-255 but is clamped to 239.
> + * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
> + * 6.3125 in 4.4 format is b01100101 which is equal to 101.
> + * Also 85 + 16 = 101.
> + */
> + crtc_state->hw.casf_params.strength =
> + min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
> +
> + intel_casf_compute_win_size(crtc_state);
> +
> + return 0;
> +}
> +
> +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + u32 sharp;
> +
> + sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
> + if (sharp & FILTER_EN) {
> + if (drm_WARN_ON(display->drm,
> + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
> + crtc_state->hw.casf_params.strength = 0;
> + else
> + crtc_state->hw.casf_params.strength =
> + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
> + crtc_state->hw.casf_params.casf_enable = true;
> + crtc_state->hw.casf_params.win_size =
> + REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h
> new file mode 100644
> index 000000000000..83523fe66c48
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_casf.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CASF_H__
> +#define __INTEL_CASF_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_crtc_state;
> +
> +int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
> +void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
> +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
> +
> +#endif /* __INTEL_CASF_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> new file mode 100644
> index 000000000000..c24ba281ae37
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CASF_REGS_H__
> +#define __INTEL_CASF_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _SHARPNESS_CTL_A 0x682B0
> +#define _SHARPNESS_CTL_B 0x68AB0
> +#define SHARPNESS_CTL(pipe) _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
> +#define FILTER_EN REG_BIT(31)
> +#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8)
> +#define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
> +#define FILTER_SIZE_MASK REG_GENMASK(1, 0)
> +#define SHARPNESS_FILTER_SIZE_3X3 REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
> +#define SHARPNESS_FILTER_SIZE_5X5 REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
> +#define SHARPNESS_FILTER_SIZE_7X7 REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
> +
> +#endif /* __INTEL_CASF_REGS__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 599ddce96371..66b6fbae8294 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -372,6 +372,13 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>
> intel_vdsc_state_dump(&p, 0, pipe_config);
>
> + if (HAS_CASF(i915)) {
> + drm_printf(&p, "sharpness strength: %d, sharpness tap size :%d\n sharpness enable :%d\n",
> + pipe_config->hw.casf_params.strength,
> + pipe_config->hw.casf_params.win_size,
> + pipe_config->hw.casf_params.casf_enable);
> + }
> +
> dump_planes:
> if (!state)
> return;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 7d9cc430a6b8..2540a2a1a0e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -931,6 +931,12 @@ struct intel_csc_matrix {
> u16 postoff[3];
> };
>
> +struct intel_casf {
> + u8 strength;
> + u8 win_size;
> + bool casf_enable;
> +};
> +
> void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
>
> typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
> @@ -971,6 +977,7 @@ struct intel_crtc_state {
> struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> struct drm_display_mode mode, pipe_mode, adjusted_mode;
> enum drm_scaling_filter scaling_filter;
> + struct intel_casf casf_params;
> } hw;
>
> /* actual state of LUTs */
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index ee81220a7c88..f0cf966211c9 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -5,6 +5,7 @@
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "intel_casf_regs.h"
> #include "intel_de.h"
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index cd464fe26eb8..785bda98973d 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -210,6 +210,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_backlight.o \
> i915-display/intel_bios.o \
> i915-display/intel_bw.o \
> + i915-display/intel_casf.o \
> i915-display/intel_cdclk.o \
> i915-display/intel_cmtg.o \
> i915-display/intel_color.o \
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