[PATCH v3 01/15] clk: renesas: rzv2h-cpg: Add support for DSI clocks

[ALOK TIWARI]

On 19-04-2025 00:16, Prabhakar wrote:
> + * @freq: Target output frequency (in mHz)

Do you mind checking this one

> + *
> + * This function calculates the best set of PLL parameters (M, K, P, S) and divider
> + * value (CSDIV) to achieve the desired frequency.
> + * There is no direct formula to calculate the PLL parameters and the divider value,
> + * as it's an open system of equations, therefore this function uses an iterative
> + * approach to determine the best solution. The best solution

Thanks,
Alok