[PATCH v3 10/15] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations
Lad, Prabhakar
prabhakar.csengg at gmail.com
Wed Apr 23 11:53:58 UTC 2025
Hi Geert,
Thank you for the review.
On Tue, Apr 22, 2025 at 8:41 AM Geert Uytterhoeven <geert at linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, 18 Apr 2025 at 20:47, Prabhakar <prabhakar.csengg at gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> >
> > Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
> > precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
> > high accuracy.
> >
> > These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
> >
> > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz at renesas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz at renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > ---
> > v2->v3:
> > - Replaced `unsigned long long` with `u64`
> > - Replaced *_mhz with *_millihz` in functions
>
> Thanks for the update!
>
> > @@ -203,8 +203,9 @@ static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
> > */
> >
> > static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
> > - unsigned long hsfreq)
> > + u64 hsfreq_millihz)
> > {
> > + unsigned long hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, KILO);
>
> MILLI (everywhere)
>
OK.
> It's a strange world where KILO == MILLI ;-)
>
:-)
> include/linux/units.h:#define KILO 1000UL
> include/linux/units.h-#define MILLI 1000UL
>
> > const struct rzg2l_mipi_dsi_timings *dphy_timings;
> > unsigned int i;
> > u32 dphyctrl0;
> > @@ -277,6 +278,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
> > const struct drm_display_mode *mode)
> > {
> > unsigned long hsfreq, vclk_rate;
> > + u64 hsfreq_millihz;
> > unsigned int bpp;
> > u32 txsetr;
> > u32 clstptsetr;
> > @@ -305,9 +307,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
> > */
> > bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> > vclk_rate = clk_get_rate(dsi->vclk);
> > - hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes);
> > + hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp * KILO * 1ULL, dsi->lanes);
>
> The "* 1ULL" only makes the last factor unsigned long long.
> "vclk_rate * bpp" is still unsigned long, causing overflow on 32-bit.
> As there is no rounding variant of mul_u64_u32_div(), you probably
> want to use mul_u32_u32() instead.
>
Agreed, I will update it to,
`DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * KILO),
dsi->lanes);`
Cheers,
Prabhakar
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