[PATCH v2 2/6] drm/i915/gt: Move CCS workaround to the correct section

[Lucas De Marchi]

On Thu, Mar 27, 2025 at 12:40:01AM +0100, Andi Shyti wrote:
>The CCS engine workaround was previously added in a section
>shared by both RCS and CCS engines.
>
>Move it to the proper CCS-specific section so that it's applied
>only once, avoiding unintended duplication caused by the first
>CCS/RCS detection check.
>
>To do this, the ccs_mode() function had to be moved earlier in
>the file to avoid the need for a forward declaration.
>
>Suggested-by: Arshad Mehmood <arshad.mehmood at intel.com>
>Signed-off-by: Andi Shyti <andi.shyti at linux.intel.com>

I'm not sure about this one. I think it was done like this because
the register exists on render and has no side effect setting it there.

>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 58 +++++++++++----------
> 1 file changed, 30 insertions(+), 28 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index 116683ebe074..bedd88a15959 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -2699,10 +2699,38 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> 				    XEHP_BLITTER_ROUND_ROBIN_MODE);
> }
>
>+static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>+{
>+	struct intel_gt *gt = engine->gt;
>+	u32 mode;
>+
>+	/*
>+	 * This workaround should be applied only once across all
>+	 * CCS engines. Apply it to the first CCS encountered.
>+	 */
>+	if (!FIRST_CCS(engine))

the problem you'd face is that if you fix this macro to also include
render, then you break it here.

Lucas De Marchi

>+		return;
>+
>+	/*
>+	 * Wa_14019159160: This workaround, along with others, leads to
>+	 * significant challenges in utilizing load balancing among the
>+	 * CCS slices. Consequently, an architectural decision has been
>+	 * made to completely disable automatic CCS load balancing.
>+	 */
>+	wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
>+
>+	/*
>+	 * After having disabled automatic load balancing we need to
>+	 * assign all slices to a single CCS. We will call it CCS mode 1
>+	 */
>+	mode = intel_gt_apply_ccs_mode(gt);
>+	wa_masked_en(wal, XEHP_CCS_MODE, mode);
>+}
>+
> static void
> ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
>-	/* boilerplate for any CCS engine workaround */
>+	ccs_engine_wa_mode(engine, wal);
> }
>
> /*
>@@ -2739,30 +2767,6 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
> 		wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
> }
>
>-static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>-{
>-	struct intel_gt *gt = engine->gt;
>-	u32 mode;
>-
>-	if (!IS_DG2(gt->i915))
>-		return;
>-
>-	/*
>-	 * Wa_14019159160: This workaround, along with others, leads to
>-	 * significant challenges in utilizing load balancing among the
>-	 * CCS slices. Consequently, an architectural decision has been
>-	 * made to completely disable automatic CCS load balancing.
>-	 */
>-	wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
>-
>-	/*
>-	 * After having disabled automatic load balancing we need to
>-	 * assign all slices to a single CCS. We will call it CCS mode 1
>-	 */
>-	mode = intel_gt_apply_ccs_mode(gt);
>-	wa_masked_en(wal, XEHP_CCS_MODE, mode);
>-}
>-
> /*
>  * The workarounds in this function apply to shared registers in
>  * the general render reset domain that aren't tied to a
>@@ -2895,10 +2899,8 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
> 	 * to a single RCS/CCS engine's workaround list since
> 	 * they're reset as part of the general render domain reset.
> 	 */
>-	if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) {
>+	if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
> 		general_render_compute_wa_init(engine, wal);
>-		ccs_engine_wa_mode(engine, wal);
>-	}
>
> 	if (engine->class == COMPUTE_CLASS)
> 		ccs_engine_wa_init(engine, wal);
>-- 
>2.47.2
>