drm/panfrost: question about cache coherency handling

[Gregory Greenman]

Hello,

I'm new to DRM development and ran into something in the Panfrost (but also Panthor) driver I'm curious about.

In drivers/gpu/drm/panfrost/panfrost_gem.c, there's this line: obj->base.map_wc = !pfdev->coherent;
>From what I can tell, this means when the CPU isn't coherent, it uses write-combining mapping.

I'm wondering why this approach instead of something like the dma_sync_single_* functions at the appropriate places?

Thanks,
Gregory
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