[PATCH 0/4] drm/tidss: Fixes data edge sampling

[devarsh]

Hi Tomi, Louis,

On 07/08/25 18:51, Tomi Valkeinen wrote:
> Hi,
> 
> On 30/07/2025 20:02, Louis Chauvet wrote:
>> Currently the driver only configure the data edge sampling partially. The 
>> AM62 require it to be configured in two distincts registers: one in tidss 
>> and one in the general device registers.
>>
>> Introduce a new dt property to link the proper syscon node from the main 
>> device registers into the tidss driver.
>>
>> Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem")
>> ---
>> Cc: stable at vger.kernel.org
>>
>> Signed-off-by: Louis Chauvet <louis.chauvet at bootlin.com>
> 
> I understand why you call this a fix, but I think this is not really a
> fix. From looking at the patches, my understanding is that for DPI
> outputs we have always only supported certain clock/data edge.

I don't think driver makes a distinction between supported/unsupported
or errors out in case it is run with "different" clock/data edge panel
(for e.g  DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE is set per the panel
configuration). Instead it tries to program the VP registers per the
DRM_BUS_FLAG* getting passed by framework per the connected panel and
gives an incorrect behavior if those are different than defaults since
those settings are not sufficient for these displays and instead extra
MMR register settings are also required.

 So this
> series is adding a new feature to the driver.
> 

I think it is a bug due to above mentioned behavior, and good to have a
Fixes tag.

Regards
Devarsh