[PATCH] nouveau/fence: handle cross device fences properly. (v3)

[kernel test robot]

Hi Dave,

kernel test robot noticed the following build errors:

[auto build test ERROR on linus/master]
[also build test ERROR on drm-misc/drm-misc-next drm-tip/drm-tip v6.13-rc6 next-20250109]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Dave-Airlie/nouveau-fence-handle-cross-device-fences-properly-v3/20250109-085805
base:   linus/master
patch link:    https://lore.kernel.org/r/20250109005553.623947-1-airlied%40gmail.com
patch subject: [PATCH] nouveau/fence: handle cross device fences properly. (v3)
config: loongarch-randconfig-002-20250110 (https://download.01.org/0day-ci/archive/20250110/202501101033.wlEjeZwK-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250110/202501101033.wlEjeZwK-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501101033.wlEjeZwK-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/gpu/drm/nouveau/nouveau_fence.c: In function 'nouveau_fence_sync':
>> drivers/gpu/drm/nouveau/nouveau_fence.c:394:53: error: 'struct nouveau_channel' has no member named 'drm'
     394 |                                 local = prev && prev->drm == chan->drm;
         |                                                     ^~
   drivers/gpu/drm/nouveau/nouveau_fence.c:394:66: error: 'struct nouveau_channel' has no member named 'drm'
     394 |                                 local = prev && prev->drm == chan->drm;
         |                                                                  ^~


vim +394 drivers/gpu/drm/nouveau/nouveau_fence.c

   356	
   357	int
   358	nouveau_fence_sync(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
   359			   bool exclusive, bool intr)
   360	{
   361		struct nouveau_fence_chan *fctx = chan->fence;
   362		struct dma_resv *resv = nvbo->bo.base.resv;
   363		int i, ret;
   364	
   365		ret = dma_resv_reserve_fences(resv, 1);
   366		if (ret)
   367			return ret;
   368	
   369		/* Waiting for the writes first causes performance regressions
   370		 * under some circumstances. So manually wait for the reads first.
   371		 */
   372		for (i = 0; i < 2; ++i) {
   373			struct dma_resv_iter cursor;
   374			struct dma_fence *fence;
   375	
   376			dma_resv_for_each_fence(&cursor, resv,
   377						dma_resv_usage_rw(exclusive),
   378						fence) {
   379				enum dma_resv_usage usage;
   380				struct nouveau_fence *f;
   381	
   382				usage = dma_resv_iter_usage(&cursor);
   383				if (i == 0 && usage == DMA_RESV_USAGE_WRITE)
   384					continue;
   385	
   386				f = nouveau_local_fence(fence, chan->cli->drm);
   387				if (f) {
   388					struct nouveau_channel *prev;
   389					bool must_wait = true;
   390					bool local;
   391	
   392					rcu_read_lock();
   393					prev = rcu_dereference(f->channel);
 > 394					local = prev && prev->drm == chan->drm;
   395					if (local && (prev == chan ||
   396						      fctx->sync(f, prev, chan) == 0))
   397						must_wait = false;
   398					rcu_read_unlock();
   399					if (!must_wait)
   400						continue;
   401				}
   402	
   403				ret = dma_fence_wait(fence, intr);
   404				if (ret)
   405					return ret;
   406			}
   407		}
   408	
   409		return 0;
   410	}
   411	

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