[PATCH 08/10] drm/ast: Split ast_set_def_ext_reg() by chip generation
Jocelyn Falempe
jfalempe at redhat.com
Thu Jul 3 13:11:28 UTC 2025
On 02/07/2025 15:12, Thomas Zimmermann wrote:
> Duplicate ast_set_def_ext_reg() for individual chip generations
> and move call it into per-chip source files. Remove the original
> code. AST2100 and AST2500 reuse the function from earlier chips.
> AST2600 appears to be incorrect as it uses an older function. Keep
> this behavior for now.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe <jfalempe at redhat.com>
>
> Signed-off-by: Thomas Zimmermann <tzimmermann at suse.de>
> ---
> drivers/gpu/drm/ast/ast_2000.c | 32 +++++++++++++++++++++++++++
> drivers/gpu/drm/ast/ast_2100.c | 2 ++
> drivers/gpu/drm/ast/ast_2300.c | 33 ++++++++++++++++++++++++++++
> drivers/gpu/drm/ast/ast_2500.c | 2 ++
> drivers/gpu/drm/ast/ast_2600.c | 33 ++++++++++++++++++++++++++++
> drivers/gpu/drm/ast/ast_post.c | 40 ----------------------------------
> drivers/gpu/drm/ast/ast_post.h | 9 ++++++++
> 7 files changed, 111 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/ast/ast_2000.c b/drivers/gpu/drm/ast/ast_2000.c
> index 93f13ecc74dc..41c2aa1e425a 100644
> --- a/drivers/gpu/drm/ast/ast_2000.c
> +++ b/drivers/gpu/drm/ast/ast_2000.c
> @@ -35,6 +35,36 @@
> * POST
> */
>
> +void ast_2000_set_def_ext_reg(struct ast_device *ast)
> +{
> + static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
> + u8 i, index, reg;
> + const u8 *ext_reg_info;
> +
> + /* reset scratch */
> + for (i = 0x81; i <= 0x9f; i++)
> + ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
> +
> + ext_reg_info = extreginfo;
> + index = 0xa0;
> + while (*ext_reg_info != 0xff) {
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
> + index++;
> + ext_reg_info++;
> + }
> +
> + /* disable standard IO/MEM decode if secondary */
> + /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
> +
> + /* Set Ext. Default */
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
> +
> + /* Enable RAMDAC for A1 */
> + reg = 0x04;
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
> +}
> +
> static const struct ast_dramstruct ast2000_dram_table_data[] = {
> { 0x0108, 0x00000000 },
> { 0x0120, 0x00004a21 },
> @@ -104,6 +134,8 @@ static void ast_post_chip_2000(struct ast_device *ast)
>
> int ast_2000_post(struct ast_device *ast)
> {
> + ast_2000_set_def_ext_reg(ast);
> +
> if (ast->config_mode == ast_use_p2a) {
> ast_post_chip_2000(ast);
> } else {
> diff --git a/drivers/gpu/drm/ast/ast_2100.c b/drivers/gpu/drm/ast/ast_2100.c
> index 1cabac647584..477ee15eff5d 100644
> --- a/drivers/gpu/drm/ast/ast_2100.c
> +++ b/drivers/gpu/drm/ast/ast_2100.c
> @@ -333,6 +333,8 @@ static void ast_post_chip_2100(struct ast_device *ast)
>
> int ast_2100_post(struct ast_device *ast)
> {
> + ast_2000_set_def_ext_reg(ast);
> +
> if (ast->config_mode == ast_use_p2a) {
> ast_post_chip_2100(ast);
> } else {
> diff --git a/drivers/gpu/drm/ast/ast_2300.c b/drivers/gpu/drm/ast/ast_2300.c
> index 7a2c3fde09d2..dc2a32244689 100644
> --- a/drivers/gpu/drm/ast/ast_2300.c
> +++ b/drivers/gpu/drm/ast/ast_2300.c
> @@ -35,6 +35,37 @@
> * POST
> */
>
> +void ast_2300_set_def_ext_reg(struct ast_device *ast)
> +{
> + static const u8 extreginfo[] = { 0x0f, 0x04, 0x1f, 0xff };
> + u8 i, index, reg;
> + const u8 *ext_reg_info;
> +
> + /* reset scratch */
> + for (i = 0x81; i <= 0x9f; i++)
> + ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
> +
> + ext_reg_info = extreginfo;
> + index = 0xa0;
> + while (*ext_reg_info != 0xff) {
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
> + index++;
> + ext_reg_info++;
> + }
> +
> + /* disable standard IO/MEM decode if secondary */
> + /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
> +
> + /* Set Ext. Default */
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
> +
> + /* Enable RAMDAC for A1 */
> + reg = 0x04;
> + reg |= 0x20;
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
> +}
> +
> /* AST 2300 DRAM settings */
> #define AST_DDR3 0
> #define AST_DDR2 1
> @@ -1281,6 +1312,8 @@ static void ast_post_chip_2300(struct ast_device *ast)
>
> int ast_2300_post(struct ast_device *ast)
> {
> + ast_2300_set_def_ext_reg(ast);
> +
> if (ast->config_mode == ast_use_p2a) {
> ast_post_chip_2300(ast);
> ast_init_3rdtx(ast);
> diff --git a/drivers/gpu/drm/ast/ast_2500.c b/drivers/gpu/drm/ast/ast_2500.c
> index e5b3e0c63222..1e541498ea67 100644
> --- a/drivers/gpu/drm/ast/ast_2500.c
> +++ b/drivers/gpu/drm/ast/ast_2500.c
> @@ -554,6 +554,8 @@ static void ast_post_chip_2500(struct ast_device *ast)
>
> int ast_2500_post(struct ast_device *ast)
> {
> + ast_2300_set_def_ext_reg(ast);
> +
> if (ast->config_mode == ast_use_p2a) {
> ast_post_chip_2500(ast);
> } else {
> diff --git a/drivers/gpu/drm/ast/ast_2600.c b/drivers/gpu/drm/ast/ast_2600.c
> index 556571efa0b2..f9b96c631d4c 100644
> --- a/drivers/gpu/drm/ast/ast_2600.c
> +++ b/drivers/gpu/drm/ast/ast_2600.c
> @@ -27,15 +27,48 @@
> */
>
> #include "ast_drv.h"
> +#include "ast_post.h"
>
> /*
> * POST
> */
>
> +void ast_2600_set_def_ext_reg(struct ast_device *ast)
> +{
> + static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
> + u8 i, index, reg;
> + const u8 *ext_reg_info;
> +
> + /* reset scratch */
> + for (i = 0x81; i <= 0x9f; i++)
> + ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
> +
> + ext_reg_info = extreginfo;
> + index = 0xa0;
> + while (*ext_reg_info != 0xff) {
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
> + index++;
> + ext_reg_info++;
> + }
> +
> + /* disable standard IO/MEM decode if secondary */
> + /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
> +
> + /* Set Ext. Default */
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
> +
> + /* Enable RAMDAC for A1 */
> + reg = 0x04;
> + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
> +}
> +
> int ast_2600_post(struct ast_device *ast)
> {
> int ret;
>
> + ast_2600_set_def_ext_reg(ast);
> +
> if (ast->tx_chip == AST_TX_ASTDP) {
> ret = ast_dp_launch(ast);
> if (ret)
> diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
> index 8e575e713f19..b72914dbed38 100644
> --- a/drivers/gpu/drm/ast/ast_post.c
> +++ b/drivers/gpu/drm/ast/ast_post.c
> @@ -34,44 +34,6 @@
> #include "ast_drv.h"
> #include "ast_post.h"
>
> -static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
> -static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
> -
> -static void ast_set_def_ext_reg(struct ast_device *ast)
> -{
> - u8 i, index, reg;
> - const u8 *ext_reg_info;
> -
> - /* reset scratch */
> - for (i = 0x81; i <= 0x9f; i++)
> - ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
> -
> - if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
> - ext_reg_info = extreginfo_ast2300;
> - else
> - ext_reg_info = extreginfo;
> -
> - index = 0xa0;
> - while (*ext_reg_info != 0xff) {
> - ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
> - index++;
> - ext_reg_info++;
> - }
> -
> - /* disable standard IO/MEM decode if secondary */
> - /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
> -
> - /* Set Ext. Default */
> - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
> - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
> -
> - /* Enable RAMDAC for A1 */
> - reg = 0x04;
> - if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
> - reg |= 0x20;
> - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
> -}
> -
> u32 __ast_mindwm(void __iomem *regs, u32 r)
> {
> u32 data;
> @@ -114,8 +76,6 @@ int ast_post_gpu(struct ast_device *ast)
> {
> int ret;
>
> - ast_set_def_ext_reg(ast);
> -
> if (AST_GEN(ast) >= 7) {
> ret = ast_2600_post(ast);
> if (ret)
> diff --git a/drivers/gpu/drm/ast/ast_post.h b/drivers/gpu/drm/ast/ast_post.h
> index 44136856952f..9f3108ddeae8 100644
> --- a/drivers/gpu/drm/ast/ast_post.h
> +++ b/drivers/gpu/drm/ast/ast_post.h
> @@ -41,4 +41,13 @@ void __ast_moutdwm(void __iomem *regs, u32 r, u32 v);
> bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl);
> bool mmc_test_burst(struct ast_device *ast, u32 datagen);
>
> +/* ast_2000.c */
> +void ast_2000_set_def_ext_reg(struct ast_device *ast);
> +
> +/* ast_2300.c */
> +void ast_2300_set_def_ext_reg(struct ast_device *ast);
> +
> +/* ast_2600.c */
> +void ast_2600_set_def_ext_reg(struct ast_device *ast);
> +
> #endif
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